VERTICAL NONVOLATILE MEMORY DEVICE INCLUDING MEMORY CELL STRING

    公开(公告)号:US20210217473A1

    公开(公告)日:2021-07-15

    申请号:US17146999

    申请日:2021-01-12

    Abstract: A vertical nonvolatile memory device including a memory cell string using a resistance change material is disclosed. Each memory cell string of the nonvolatile memory device includes a semiconductor layer extending in a first direction and having a first surface opposite a second surface, a plurality of gates and a plurality of insulators alternately arranged in the first direction and extending in a second direction perpendicular to the first direction, a gate insulating layer extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer, and a dielectric film extending in the first direction on the surface of the semiconductor layer and having a plurality of movable oxygen vacancies distributed therein.

    VARIABLE RESISTANCE MEMORY DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME

    公开(公告)号:US20240196763A1

    公开(公告)日:2024-06-13

    申请号:US18214755

    申请日:2023-06-27

    CPC classification number: H10N70/826 H10B63/84 H10N70/8833

    Abstract: A variable resistance memory device includes a pillar, a resistance change layer provided at a side surface of the pillar, a semiconductor layer provided at a side surface of the resistance change layer, a gate insulating layer provided at a side surface of the semiconductor layer, a plurality of isolating layers and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer, and an internal resistance layer between the resistance change layer and the semiconductor layer, where a resistance of the internal resistance layer is greater than a resistance of the semiconductor layer when the semiconductor layer includes conductor characteristics and the resistance of the internal resistance layer is less than the resistance of the semiconductor layer when the semiconductor layer includes insulator characteristics.

    MEMORY DEVICE INCLUDING VERTICAL STACK STRUCTURE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20220310827A1

    公开(公告)日:2022-09-29

    申请号:US17459527

    申请日:2021-08-27

    Abstract: Disclosed are a memory device including a vertical stack structure and a method of manufacturing the memory device. The memory device includes an insulating structure having a shape including a first surface and a protrusion portion protruding in a first direction from the first surface, a recording material layer covering the protrusion portion along a protruding shape of the protrusion portion and extending to the first surface on the insulating structure a channel layer on the recording material layer along a surface of the recording material layer, a gate insulating layer on the channel layer, and a gate electrode formed at a location on the gate insulating layer to face a second surface which is a protruding upper surface of the protrusion portion, wherein a void exists between the gate electrode and the insulating structure, defined by the insulating structure and the recording material layer.

    MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20220077235A1

    公开(公告)日:2022-03-10

    申请号:US17317154

    申请日:2021-05-11

    Abstract: A memory device may include an insulating structure including a first surface and a protrusion portion protruding from the first surface in a first direction, a recording material layer on the insulating structure and extending along a protruding surface of the protrusion portion to cover the protrusion portion and extending onto the first surface of the insulating structure, a channel layer on the recording material layer and extending along a surface of the recording material layer, a gate insulating layer on the channel layer; and a gate electrode formed on the gate insulating layer at a location facing a second surface of the insulating structure. The second surface of the insulating structure may be a protruding upper surface of the protrusion portion.

    VERTICAL NONVOLATILE MEMORY DEVICE INCLUDING MEMORY CELL STRING

    公开(公告)号:US20220020818A1

    公开(公告)日:2022-01-20

    申请号:US17345423

    申请日:2021-06-11

    Abstract: A vertical nonvolatile memory device including memory cell strings using a resistance change material is provided. Each of the memory cell strings of the nonvolatile memory device includes a semiconductor layer extending in a first direction; a plurality of gates and a plurality of insulators alternately arranged in the first direction; a gate insulating layer extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer; and a resistance change layer extending in the first direction on a surface of the semiconductor layer. The resistance change layer includes a metal-semiconductor oxide including a mixture of a semiconductor material of the semiconductor layer and a transition metal oxide.

    NON-VOLATILE MEMORY DEVICE AND OPERATING METHOD OF THE SAME

    公开(公告)号:US20210035641A1

    公开(公告)日:2021-02-04

    申请号:US16775424

    申请日:2020-01-29

    Abstract: Provided are a non-volatile memory device and an operating method thereof. The non-volatile memory device includes a memory cell array having a vertically stacked structure, a bit line for applying a programming voltage to the memory cell array, and a control logic. The memory cell array includes memory cells that each include a corresponding portion of a semiconductor layer and a corresponding portion of a resistance layer. The memory cells include a non-selected memory cell, a compensation memory cell, and a selected memory cell. The control logic is configured to apply an adjusted program voltage to the selected memory cell, based on applying a first voltage to the compensation memory cell, a second voltage to the selected memory cell, and a third voltage to the non-selected memory cell. The adjusted program voltage may be dropped compared to the programming voltage due to the compensation memory cell.

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