公开(公告)号：US11721727B2

公开(公告)日：2023-08-08

申请号：US17001117

申请日：2020-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Peter Rabkin

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/417 ,  H01L21/28 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L29/41741 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/40114 ,  H01L29/40117 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.

公开(公告)号：US11374020B2

公开(公告)日：2022-06-28

申请号：US16887659

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Peter Rabkin ,  Raghuveer S. Makala

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/207 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11556 ,  H01L27/11519

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

公开(公告)号：US11063063B2

公开(公告)日：2021-07-13

申请号：US16710481

申请日：2019-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Dong-il Moon ,  Raghuveer S. Makala ,  Peng Zhang ,  Wei Zhao ,  Ashish Baraskar

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/532 ,  H01L21/311 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/28 ,  H01L23/528 ,  H01L27/11519

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

公开(公告)号：US11024387B2

公开(公告)日：2021-06-01

申请号：US17102712

申请日：2020-11-24

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C11/56 ,  G11C16/26

Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.

公开(公告)号：US20200335168A1

公开(公告)日：2020-10-22

申请号：US16922037

申请日：2020-07-07

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C16/14 ,  G11C16/34 ,  H01L27/1157 ,  G11C16/04 ,  H01L27/11578

Abstract: Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.

公开(公告)号：US20200243141A1

公开(公告)日：2020-07-30

申请号：US16847377

申请日：2020-04-13

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C16/10 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/1157 ,  G11C16/34

Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.

公开(公告)号：US11322509B2

公开(公告)日：2022-05-03

申请号：US17001270

申请日：2020-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Peter Rabkin

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L21/8239 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10

Abstract: A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.

公开(公告)号：US11244734B2

公开(公告)日：2022-02-08

申请号：US16728716

申请日：2019-12-27

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Henry Chin ,  Ching-Huang Lu

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  G11C16/26

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells coupled to a control circuit. The control circuit is configured to perform a first programming stage including iteratively programming each of the memory cells to first program states and verifying that the memory cells have a threshold voltage above one of a plurality of first verify voltages corresponding to the first program states. The first programming stage ends before all of the memory cells are verified thereby leaving a fraction of the memory cells below the one of the plurality of first verify voltages. The control circuit also performs a second programming stage including iteratively programming each of the memory cells to second program states and verifying that at least a predetermined number of the memory cells have the threshold voltage above one of a plurality of second verify voltages corresponding to the second program states.

公开(公告)号：US10923197B2

公开(公告)日：2021-02-16

申请号：US16922037

申请日：2020-07-07

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  G11C16/34 ,  H01L27/11578

Abstract: Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.

公开(公告)号：US10741253B1

公开(公告)日：2020-08-11

申请号：US16280297

申请日：2019-02-20

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C7/00 ,  G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  G11C16/34 ,  H01L27/11578

Abstract: Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.