公开(公告)号：US20180122905A1

公开(公告)日：2018-05-03

申请号：US15458269

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Kazuyo Matsumoto ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.

公开(公告)号：US09953992B1

公开(公告)日：2018-04-24

申请号：US15611220

申请日：2017-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  James Kai

IPC: H01L29/792 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

Abstract: A three-dimensional memory array device can include mid-plane terrace regions between a pair of memory array regions. The electrically conductive layers of the three-dimensional memory array device continuously extend between the pair of memory array regions through a connection region, which is provided adjacent to the mid-plane terrace regions. Contact via structures contacting the electrically conductive layers can be provided in the mid-plane terrace regions, and through-memory-level via structures that extend through the alternating stack and connected to underlying lower metal interconnect structures and semiconductor devices can be provided through the mid-plane terrace region and/or through the connection region. Upper metal interconnect structures can connect the contact via structures and the through-memory-level via structures.

公开(公告)号：US09824966B1

公开(公告)日：2017-11-21

申请号：US15235864

申请日：2016-08-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Senaka Kanakamedala ,  Raghuveer S. Makala ,  Yanli Zhang ,  Rahul Sharangpani ,  James Kai ,  Yao-Sheng Lee

IPC: H01L29/74 ,  H01L29/76 ,  H01L21/00 ,  H01L21/337 ,  H01L21/8238 ,  H01L21/8236 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A sacrificial film and an alternating stack of insulating layers and sacrificial material layers are sequentially formed over a substrate. A memory stack structure including a memory film and a vertical semiconductor channel is formed through the alternating stack and the sacrificial film on the substrate. A source level cavity is formed by introducing an etchant or a reactant through a backside trench and removing the sacrificial film. After removal of an annular portion of the memory film, a portion of the vertical semiconductor channel is converted into an annular source region by introducing electrical dopants into the channel. A source contact layer is formed in the source level cavity and directly on the annular source region. The sacrificial material layers are replaced with electrically conductive layers. The annular source region and the source contact layer can provide low source contact resistance in a three-dimensional NAND memory device.

公开(公告)号：US09818693B2

公开(公告)日：2017-11-14

申请号：US15269017

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumiaki Toyama ,  Hiroyuki Ogawa ,  Yoko Furihata ,  James Kai ,  Yuki Mizutani ,  Jixin Yu ,  Jin Liu ,  Johann Alsmeier

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US09805805B1

公开(公告)日：2017-10-31

申请号：US15244428

申请日：2016-08-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Johann Alsmeier ,  James Kai

IPC: H01L29/778 ,  H01L27/115 ,  H01L29/51 ,  G11C16/14 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573 ,  H01L21/768 ,  H01L21/265 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/14 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/26513 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A buried source semiconductor layer and p-doped semiconductor material portions are formed over a first portion of a substrate. The buried source semiconductor layer is an n-doped semiconductor material, and the p-doped semiconductor material portions are embedded within the buried source semiconductor layer. An alternating stack of insulating layers and spacer material layers is formed over the substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are formed as, or are replaced with, electrically conductive layers. The buried source semiconductor layer may be formed prior to, or after, formation of the alternating stack. The buried source semiconductor layer underlies the alternating stack and overlies the first portion of the substrate, and contacts at least one surface of the vertical semiconductor channels. The p-doped semiconductor material portions contact at least one surface of a respective subset of the vertical semiconductor channels.

公开(公告)号：US20170148810A1

公开(公告)日：2017-05-25

申请号：US15225492

申请日：2016-08-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Johann Alsmeier ,  Jin Liu ,  Yanli Zhang

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/768 ,  H01L29/423 ,  H01L23/535 ,  H01L21/306

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/30604 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42344

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. An alternating sequence of support pedestal structures and conductive rail structures extending along a same horizontal direction are provided between the substrate and the alternating stack. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support pedestal structure. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure, and is electrically isolated from an adjacent support pedestal structure by a portion of a memory film. The conductive rail structures can function as source regions of memory device.

公开(公告)号：US11587920B2

公开(公告)日：2023-02-21

申请号：US16936047

申请日：2020-07-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Johann Alsmeier ,  James Kai ,  Koichi Matsuno

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L27/11582 ,  H01L27/11556

Abstract: A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.

公开(公告)号：US11481154B2

公开(公告)日：2022-10-25

申请号：US17149867

申请日：2021-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  James Kai ,  Johann Alsmeier ,  Jian Chen

IPC: G06F3/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/11565

Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.

公开(公告)号：US11018153B2

公开(公告)日：2021-05-25

申请号：US16539103

申请日：2019-08-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Johann Alsmeier ,  Murshed Chowdhury

IPC: H01L27/11582 ,  H01L29/417 ,  H01L27/11597 ,  H01L29/10

Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, gate electrodes vertically extending through each of the source layers and the drain layers of the alternating stack, memory films laterally surrounding a respective one of the gate electrodes, and semiconductor channels laterally surrounding a respective one of the memory films and connected to a respective vertically neighboring pair of a source layer and a drain layer. An array of memory openings can vertically extend through the alternating stack, and each of the gate electrodes can be located within a respective one of the memory openings.

公开(公告)号：US10825827B2

公开(公告)日：2020-11-03

申请号：US16141149

申请日：2018-09-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mohan Dunga ,  James Kai ,  Venkatesh P. Ramachandra ,  Piyush Dak ,  Luisa Lin ,  Masaaki Higashitani

IPC: H01L21/00 ,  H01L27/11582 ,  H01L27/11573 ,  G11C7/10 ,  G11C16/10 ,  G11C16/28 ,  H01L27/1157

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.