公开(公告)号：US10249640B2

公开(公告)日：2019-04-02

申请号：US15176674

申请日：2016-06-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Zhenyu Lu ,  Alexander Chu ,  Kensuke Yamaguchi ,  Hiroyuki Ogawa ,  Daxin Mao ,  Yan LI ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.

公开(公告)号：US10115440B2

公开(公告)日：2018-10-30

申请号：US15625848

申请日：2017-06-16

Applicant: SanDisk Technologies LLC

Inventor： Qui Nguyen ,  Alexander Chu ,  Kenneth Louie ,  Anirudh Amarnath ,  Jixin Yu ,  Yen-Lung Jason Li ,  Tai-Yuan Tseng ,  Jong Yuh

IPC: G11C8/08 ,  G11C5/06 ,  H01L27/112 ,  G11C8/10 ,  G06F13/40

Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.

公开(公告)号：US09985046B2

公开(公告)日：2018-05-29

申请号：US15180902

申请日：2016-06-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhenyu Lu ,  Jixin Yu ,  Koji Miyata ,  Makoto Yoshida ,  Johann Alsmeier ,  Hiro Kinoshita ,  Daxin Mao

IPC: H01L27/115 ,  H01L27/11582 ,  H01L21/66 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/522 ,  H01L23/544 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76801 ,  H01L22/20 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L2223/54426

Abstract: A linear mark extending perpendicular to a primary step direction of stepped terrace for a three-dimensional memory device can be employed as a reference feature for aligning a trimming material layer before initiating an etch-and-trim process sequence. The linear mark can be formed as a linear trench or a linear rail structure. The distance between a sidewall of each trimming material layer and the linear mark can be measured at multiple locations that are laterally spaced apart perpendicular to the primary step direction to provide statistically significant data points, which can be employed to provide an enhanced control of the staircase patterning process. Likewise, locations of patterned stepped surfaces can be measured at multiple locations to provide enhanced control of the locations of vertical steps in the stepped terrace.

公开(公告)号：US20180122905A1

公开(公告)日：2018-05-03

申请号：US15458269

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Kazuyo Matsumoto ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.

公开(公告)号：US09818693B2

公开(公告)日：2017-11-14

申请号：US15269017

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumiaki Toyama ,  Hiroyuki Ogawa ,  Yoko Furihata ,  James Kai ,  Yuki Mizutani ,  Jixin Yu ,  Jin Liu ,  Johann Alsmeier

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US10707228B2

公开(公告)日：2020-07-07

申请号：US16284502

申请日：2019-02-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/088 ,  H01L27/11578 ,  G11C5/02 ,  G11C5/06

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

公开(公告)号：US20200066745A1

公开(公告)日：2020-02-27

申请号：US16284502

申请日：2019-02-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/11578 ,  G11C5/06 ,  G11C5/02

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

公开(公告)号：US10269620B2

公开(公告)日：2019-04-23

申请号：US15274451

申请日：2016-09-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Zhenyu Lu ,  Hiroyuki Ogawa ,  Daxin Mao ,  Kensuke Yamaguchi ,  Sung Tae Lee ,  Yao-sheng Lee ,  Johann Alsmeier

IPC: H01L27/115 ,  H01L21/768 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11548

Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.

公开(公告)号：US10256248B2

公开(公告)日：2019-04-09

申请号：US15175450

申请日：2016-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhenyu Lu ,  Jixin Yu ,  Johann Alsmeier ,  Fumiaki Toyama ,  Yuki Mizutani ,  Hiroyuki Ogawa ,  Chun Ge ,  Daxin Mao ,  Yanli Zhang ,  Alexander Chu ,  Yan Li

IPC: H01L27/11582 ,  H01L21/48 ,  H01L23/498 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region. At least one through-memory-level via structure can be formed through the remaining portions of the spacer dielectric layers and the insulating layers to provide a vertically conductive path through a memory-level assembly.

公开(公告)号：US09985098B2

公开(公告)日：2018-05-29

申请号：US15458200

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuyo Matsumoto ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Hiroyuki Ogawa ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.