公开(公告)号：US11201111B2

公开(公告)日：2021-12-14

申请号：US16697560

申请日：2019-11-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dengtao Zhao ,  Zhiping Zhang ,  Peng Zhang ,  Deepanshu Dutta

IPC: H01L27/11578 ,  H01L23/522 ,  H01L23/528 ,  G11C5/06 ,  G11C16/16 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where the electrically conductive layers comprise word lines located between a source select gate electrode and a drain select gate electrode, a memory opening vertically extending through each layer of the alternating stack to a top surface of the substrate, a memory film and vertical semiconductor channel having a doping of a first conductivity type located in the memory opening, and an active region having a doping of a second conductivity type that is an opposite of the first conductivity type and adjoined to an end portion of the vertical semiconductor channel to provide a p-n junction. The end portion of the vertical semiconductor channel has a first thickness, and a middle portion of the vertical semiconductor channel has a second thickness which is less than the first thickness.

公开(公告)号：US11101288B2

公开(公告)日：2021-08-24

申请号：US16710572

申请日：2019-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Dong-il Moon ,  Raghuveer S. Makala ,  Peng Zhang ,  Wei Zhao ,  Ashish Baraskar

IPC: H01L27/11582 ,  H01L21/28 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

公开(公告)号：US20210134372A1

公开(公告)日：2021-05-06

申请号：US16676023

申请日：2019-11-06

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Peng Zhang ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06

Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.

公开(公告)号：US12035520B2

公开(公告)日：2024-07-09

申请号：US17485949

申请日：2021-09-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Peng Zhang

IPC: H10B41/20 ,  H10B41/10 ,  H10B41/41 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

CPC classification number: H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H10B41/10 ,  H10B43/10

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a semiconductor material layer, an inter-tier dielectric layer, and a second alternating stack of second insulating layers and second electrically conductive layers located over the inter-tier dielectric layer. A memory opening vertically extends through the second alternating stack, the inter-tier dielectric layer, and the first alternating stack. A memory opening fill structure is located in the memory opening, and includes a first vertical semiconductor channel, a second vertical semiconductor channel, and an inter-tier doped region located between the first and the second semiconductor channel, and providing a first p-n junction with the first vertical semiconductor channel and providing a second p-n junction with the second vertical semiconductor channel.

公开(公告)号：US20240145006A1

公开(公告)日：2024-05-02

申请号：US18357467

申请日：2023-07-24

Applicant: SanDisk Technologies LLC

Inventor： Peng Zhang ,  Yanli Zhang ,  Dengtao Zhao ,  Jiacen Guo

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H01L25/0657

Abstract: Memory cells of a second sub-block are programmed by pre-charging channels of unselected memory cells connected to the selected word line, boosting the pre-charged channels of unselected memory cells and applying a program voltage to selected non-volatile memory cells connected to the selected word line. The pre-charging includes applying one or more overdrive voltages to word lines connected to memory cells of a first sub-block to provide a conductive path from memory cells of the second sub-block through the first sub-block to a source line and maintaining the word lines connected to memory cells of the first sub-block at one or more overdrive voltages while ramping down signals at the end of the pre-charging. Dummy word lines, positioned between sub-blocks, are maintained at a resting voltage during the boosting in order to cut-off channels of memory cells in the second sub-block from channels of memory cells in the first sub-block.

公开(公告)号：US11871580B2

公开(公告)日：2024-01-09

申请号：US17317479

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peng Zhang ,  Yanli Zhang ,  Xiang Yang ,  Koichi Matsuno ,  Masaaki Higashitani ,  Johann Alsmeier

IPC: H10B51/30 ,  H01L21/764 ,  H01L29/06 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B51/20

CPC classification number: H10B51/30 ,  H01L21/764 ,  H01L29/0649 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B51/20

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

公开(公告)号：US11211392B1

公开(公告)日：2021-12-28

申请号：US16916186

申请日：2020-06-30

Applicant: SanDisk Technologies LLC

Inventor： Sarath Puthenthermadam ,  Yanli Zhang ,  Huai-yuan Tseng ,  Peng Zhang

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/06 ,  G11C5/06 ,  G11C5/02

Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.

公开(公告)号：US20200234778A1

公开(公告)日：2020-07-23

申请号：US16840156

申请日：2020-04-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dengtao Zhao ,  Peng Zhang ,  Nan Lu ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/12 ,  G11C8/08 ,  G11C11/408 ,  G11C16/04

Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.

公开(公告)号：US20240355401A1

公开(公告)日：2024-10-24

申请号：US18346352

申请日：2023-07-03

Applicant: SanDisk Technologies LLC

Inventor： Wei Cao ,  Xiang Yang ,  Peng Zhang

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102

Abstract: To improve programming performance in NAND memory, while maintaining programming accuracy and reducing program disturb, the channel pre-charge phase before a programming pulse can be eliminated. Instead, a read recovery phase after the program verify directly discharges a selected word line from the verify voltage to a negative word line voltage, with non-selected word lines being directly discharged from the read bypass voltage to the negative word line voltage. From the negative word line voltage, the word lines are then ramped up to ground and then on the bias levels of the following programming pulse. These conditions can drive electrons from the charge storage region of the selected memory cell, resulting in a high degree of channel boosting and much less program disturb. Variations of the technique can be applied to NAND memory operable in a sub-block mode where it can be difficult to use the typical channel pre-charge.

公开(公告)号：US20240079068A1

公开(公告)日：2024-03-07

申请号：US17939748

申请日：2022-09-07

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Deepanshu Dutta ,  Peng Zhang ,  Heguang Li

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3427 ,  G11C16/10 ,  G11C16/26

Abstract: A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks and the plurality of sub-blocks includes a first sub-block of a first subset of the block of N wordlines and a second sub-block of a second subset of the block of N wordlines; and control circuitry coupled to the block of N wordlines. The control circuitry is configured to: perform a program operation in a normal order programming sequence on the first sub-block; perform a sensing operation on the first sub-block using a reverse sensing scheme; perform a program operation in a reverse order programming sequence on the second sub-block; and perform a sensing operation on the second sub-block using a regular sensing scheme.