公开(公告)号：US20180308201A1

公开(公告)日：2018-10-25

申请号：US15494905

申请日：2017-04-24

申请人： Abhishek R. Appu ,  Altug Koker ,  Linda L. Hurd ,  Dukhwan Kim ,  Mike B. Macpherson ,  John C. Weast ,  Feng Chen ,  Farshad Akhbari ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman

发明人： Abhishek R. Appu ,  Altug Koker ,  Linda L. Hurd ,  Dukhwan Kim ,  Mike B. Macpherson ,  John C. Weast ,  Feng Chen ,  Farshad Akhbari ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman

IPC分类号： G06T1/20

CPC分类号： G06T1/20 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06F9/46 ,  G06N3/063 ,  G06T15/005 ,  G06T15/04 ,  G09G5/363

摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.

公开(公告)号：US20180285120A1

公开(公告)日：2018-10-04

申请号：US15477030

申请日：2017-04-01

申请人： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan Bhairavabhatla ,  Arthur D. Hunter, JR. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

发明人： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan Bhairavabhatla ,  Arthur D. Hunter, JR. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

IPC分类号： G06F9/38 ,  G06F9/345 ,  G06F9/30 ,  G06F12/084 ,  G06T1/60 ,  G06T1/20 ,  G09G5/36

CPC分类号： G09G5/363 ,  G06F9/461 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/455 ,  G09G5/001 ,  G09G2340/02 ,  G09G2350/00 ,  G09G2352/00 ,  G09G2360/08 ,  G09G2360/121

摘要： A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

公开(公告)号：US20180293701A1

公开(公告)日：2018-10-11

申请号：US15482680

申请日：2017-04-07

申请人： ABHISHEK R. APPU ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Pattabhiraman K ,  Matthew B. Callaway

发明人： ABHISHEK R. APPU ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Pattabhiraman K ,  Matthew B. Callaway

IPC分类号： G06T1/60 ,  G06T15/00 ,  G06F9/455 ,  G06F9/50 ,  G06F9/48

CPC分类号： G06T1/60 ,  G06F9/45558 ,  G06F9/4881 ,  G06F9/5038 ,  G06F2009/45579 ,  G06F2009/45591 ,  G06T15/005

摘要： An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

公开(公告)号：US20180299921A1

公开(公告)日：2018-10-18

申请号：US15488667

申请日：2017-04-17

申请人： Iqbal R. Rajwani ,  Altug Koker ,  Bhushan M. Borole ,  Kamal Sinha ,  Abhishek R. Appu ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Wenyin Fu

发明人： Iqbal R. Rajwani ,  Altug Koker ,  Bhushan M. Borole ,  Kamal Sinha ,  Abhishek R. Appu ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Wenyin Fu

IPC分类号： G06F1/06 ,  G06F9/38 ,  G06F13/16 ,  G06F1/08 ,  G06T1/20

CPC分类号： G06F1/06 ,  G06F1/08 ,  G06F9/30141 ,  G06F9/3869 ,  G06F13/161 ,  G06F13/1673 ,  G06T1/60 ,  H03K19/096

摘要： In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.

公开(公告)号：US20180301120A1

公开(公告)日：2018-10-18

申请号：US15488673

申请日：2017-04-17

申请人： Anupama A. Thaploo ,  Jaydeep P. Kulkarni ,  Bhushan M. Borole ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Wenyin Fu

发明人： Anupama A. Thaploo ,  Jaydeep P. Kulkarni ,  Bhushan M. Borole ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Wenyin Fu

IPC分类号： G09G5/36

摘要： In an embodiment, an apparatus includes: a repeater to receive an input signal at an input node and output an output signal at an output node; a dynamic header device coupled between the repeater and a supply voltage node; and a feedback device coupled between the output node and the dynamic header device to dynamically control the dynamic header device based at least in part on the output signal. Other embodiments are described and claimed.

公开(公告)号：US20180095785A1

公开(公告)日：2018-04-05

申请号：US15281260

申请日：2016-09-30

申请人： Altug Koker ,  Prassonkumar Surti ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Tomas G. Akenine-Moller ,  David J. Cowperthwaite ,  Balaji Vembu

发明人： Altug Koker ,  Prassonkumar Surti ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Tomas G. Akenine-Moller ,  David J. Cowperthwaite ,  Balaji Vembu

IPC分类号： G06F9/48

CPC分类号： G06F9/4831 ,  G06F9/4881

摘要： A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a thread dispatcher to assign a priority class to each of a plurality of processing threads prior to dispatching the one or more processing threads, a plurality of execution units to process the threads, a shared resource coupled to each of the plurality of execution units and an arbitration unit to grant access to the shared resource to a first of the plurality of execution units based on the priority class of a thread being executed at the first execution unit.

公开(公告)号：US20140125679A1

公开(公告)日：2014-05-08

申请号：US13669576

申请日：2012-11-06

申请人： Nikos Kaburlasos ,  Eric C. Samson ,  Altug Koker

发明人： Nikos Kaburlasos ,  Eric C. Samson ,  Altug Koker

IPC分类号： G06T1/00

CPC分类号： G06T1/20

摘要： According to some embodiments, performance bottlenecks that arise in particular resources within a graphic processor unit may be alleviated by dynamically rebalancing workloads among the resources, with the goal of removing the current performance bottleneck, while at the same time maintaining power dissipation within a currently allocated power budget. In some embodiments this may be achieved by defining a separate clock domain for each of the plurality of graphics processor resources whose performance may then be rebalanced.

摘要翻译： 根据一些实施例，可以通过动态地重新平衡资源之间的工作负载来缓解在图形处理器单元内的特定资源中出现的性能瓶颈，目的是消除当前的性能瓶颈，同时保持当前分配的 电力预算 在一些实施例中，这可以通过为多个图形处理器资源中的每个图形处理器资源定义单独的时钟域来实现，其中性能可以被重新平衡。

公开(公告)号：US20150169439A1

公开(公告)日：2015-06-18

申请号：US14133097

申请日：2013-12-18

申请人： Marc Torrant ,  David Puffer ,  Blaise Fanning ,  Bryan White ,  Joydeep Ray ,  Neil Schaper ,  Todd Witter ,  Altug Koker ,  Aditya Sreenivas

发明人： Marc Torrant ,  David Puffer ,  Blaise Fanning ,  Bryan White ,  Joydeep Ray ,  Neil Schaper ,  Todd Witter ,  Altug Koker ,  Aditya Sreenivas

IPC分类号： G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F12/126

摘要： A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.

摘要翻译： 处理设备包括指令执行单元，存储器代理和钉住逻辑，以在存储器请求时针对多级存储器系统中的存储器页面进行引脚。 钉扎逻辑包括代理接口模块，用于从存储器代理接收指示多级存储器系统中的第一存储器页的引脚请求，所述多级存储器系统包括近存储器和远存储器。 钉扎逻辑还包括存储器接口模块，用于从远端存储器检索第一存储器页面，并将第一存储器页面写入近端存储器。 此外，钉扎逻辑还包括描述符表管理模块，用于将第一存储器页标记为固定在近存储器中，其中将第一存储器页标记为固定包括将对应于第一存储器页的锁存位设置在高速缓存描述符表中 并且当第一存储器页面被标记为被固定时，防止第一存储器页被从近存储器逐出。

公开(公告)号：US20190303334A1

公开(公告)日：2019-10-03

申请号：US16447025

申请日：2019-06-20

申请人： Bryan R. White ,  Aravindh Anantaraman ,  Ankur Shah ,  Altug Koker ,  David Puffer ,  Aditya Navale

发明人： Bryan R. White ,  Aravindh Anantaraman ,  Ankur Shah ,  Altug Koker ,  David Puffer ,  Aditya Navale

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06T1/20

摘要： In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.

公开(公告)号：US20150103084A1

公开(公告)日：2015-04-16

申请号：US14050626

申请日：2013-10-10

申请人： Hema C. Nalluri ,  Aditya Navale ,  Altug Koker

发明人： Hema C. Nalluri ,  Aditya Navale ,  Altug Koker

IPC分类号： G06T1/20

CPC分类号： G06T1/20

摘要： Methods and systems may provide for storing a set of post-synchronization operations to a graphics memory and sending a flush marker to a graphics pipeline. Additionally, the set of post-synchronization operations may be processed in response to the flush marker exiting the graphics pipeline. In one example, the set of post-synchronization operations includes one or more atomic operations. Moreover, the set of post-synchronization operations may be obtained from an inline portion of an atomics command.

摘要翻译： 方法和系统可以提供将一组后同步操作存储到图形存储器并且向图形流水线发送冲洗标记。 另外，可以响应于离开图形管线的冲洗标记来处理该后同步操作的集合。 在一个示例中，该后同步操作集合包括一个或多个原子操作。 此外，可以从原子命令的内联部分获得该后同步操作的集合。