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    Differential implant oxide process
    15.
    发明授权
    Differential implant oxide process 有权
    差分植入氧化物工艺

    公开(公告)号：US06821853B1

    公开(公告)日：2004-11-23

    申请号：US10159413

    申请日：2002-05-31

    Applicant: James F. Buller ,  Scott Luning

    Inventor： James F. Buller ,  Scott Luning

    IPC: H01L218234

    CPC classification number: H01L21/823468 ,  H01L21/823462

    Abstract: Methods of manufacturing are provided. In one aspect, a method of manufacturing is provided that includes forming first and second gate stacks on a substrate and forming an insulating layer on the substrate. The insulating layer has portions adjacent to the first stack and portions adjacent to the second gate stack. A first pair of insulating structures is formed adjacent to the first gate stack and a second pair of insulating structures is formed adjacent to the second gate stack. The first pair of insulating structures is removed. The portions of the insulating layer adjacent to the first gate stack are thickened while the second pair of insulating structures prevents thickening of the portions of the insulating film adjacent to the second gate stack. Differential insulating layer thickness for different gate devices is permitted to enable reduction in leakage currents for selected devices without harming speed performance for others.

    Abstract translation: 提供制造方法。 一方面，提供一种制造方法，其包括在衬底上形成第一和第二栅极叠层并在衬底上形成绝缘层。 绝缘层具有与第一堆叠相邻的部分和与第二栅极堆叠相邻的部分。 第一对绝缘结构形成为与第一栅极堆叠相邻，并且第二对绝缘结构形成为与第二栅极堆叠相邻。 第一对绝缘结构被去除。 与第一栅极堆叠相邻的绝缘层的部分被加厚，而第二对绝缘结构防止绝缘膜的与第二栅极叠层相邻的部分的增厚。 允许不同栅极器件的差分绝缘层厚度能够减少所选器件的漏电流，而不会损害其他器件的速度性能。

    Process to separate the doping of polygate and source drain regions in dual gate field effect transistors
    16.
    发明授权
    Process to separate the doping of polygate and source drain regions in dual gate field effect transistors 失效
    在双栅场效应晶体管中分离多晶硅栅极和源极漏极区域的掺杂过程

    公开(公告)号：US06319804B1

    公开(公告)日：2001-11-20

    申请号：US08624910

    申请日：1996-03-27

    Applicant: David Greenlaw ,  Scott Luning

    Inventor： David Greenlaw ,  Scott Luning

    IPC: H01L2102

    CPC classification number: H01L29/66575 ,  H01L21/28061 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

    Abstract: The present invention is directed toward a method for independently doping the gate and the source-drain regions of a semiconductor device. The method is initiated by the provision. of a substrate having isolation regions and a thin insulating layer. Over the substrate is formed a polysilicon layer which is doped with a first type of dopant at a first doping level. Over the polysilicon layer is formed a conducting layer of material that can withstand temperatures of 1000° C., and over the conducting layer is formed a blocking layer. The polysilicon layer, the conducting layer and the blocking layer are etched to form a gate stack. Source-drain regions are subsequently doped with a second type of dopant at a second doping level. Source-drain regions are activated in a 1000° C. heat cycle, and, subsequently, TiSi2 is formed on the source-drain regions. Contacts are then formed. The blocking layer on the gate stack need not be removed, which aids in minimizing substrate damage and in prevention of shorting a source-drain contact region to the substrate.

    Abstract translation: 本发明涉及用于独立地掺杂半导体器件的栅极和源极 - 漏极区域的方法。 该方法由该条款开始。 具有隔离区域和薄绝缘层的衬底。 在衬底上形成多晶硅层，其以第一掺杂级别掺杂有第一类型的掺杂剂。 在多晶硅层上形成能够承受1000℃的温度的导电层，并且在导电层上形成阻挡层。 蚀刻多晶硅层，导电层和阻挡层以形成栅叠层。 源极 - 漏极区域随后以第二掺杂水平掺杂第二类型的掺杂剂。 源极 - 漏极区域在1000℃的热循环中被激活，随后在源极 - 漏极区域上形成TiSi 2。 然后形成接触。 栅堆叠上的阻挡层不需要去除，这有助于最小化衬底损伤并防止将源 - 漏接触区域短路到衬底。

    Shallow drain extension formation by angled implantation
    18.
    发明授权
    Shallow drain extension formation by angled implantation 失效
    通过倾斜植入形成浅层延伸

    公开(公告)号：US5935867A

    公开(公告)日：1999-08-10

    申请号：US481895

    申请日：1995-06-07

    Applicant: Roger Alvis ,  Scott Luning ,  Peter Griffin

    Inventor： Roger Alvis ,  Scott Luning ,  Peter Griffin

    IPC: H01L21/265 ,  H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L29/7835

    Abstract: A process for forming a shallow, lightly doped region in a semiconductor device. The method comprises the steps of providing a semiconductor substrate having a surface; growing an oxide layer on the substrate, the oxide having a thickness; depositing a layer of polysilicon on the oxide; patterning the polysilicon layer and the oxide layer to provide a gate structure; and implanting into the substrate a source and a drain region about the gate structure at an angle less than 90 degrees with respect to the surface of the substrate.

    Abstract translation: 一种用于在半导体器件中形成浅的，轻掺杂区域的工艺。 该方法包括提供具有表面的半导体衬底的步骤; 在衬底上生长氧化物层，氧化物具有厚度; 在氧化物上沉积多晶硅层; 图案化多晶硅层和氧化物层以提供栅极结构; 以及相对于所述衬底的表面以小于90度的角度将围绕所述栅极结构的源极和漏极区域注入到所述衬底中。

    Semiconductor device with stressed fin sections, and related fabrication methods
    19.
    发明授权
    Semiconductor device with stressed fin sections, and related fabrication methods 有权
    具有应力鳍片的半导体器件及相关制造方法

    公开(公告)号：US08030144B2

    公开(公告)日：2011-10-04

    申请号：US12576987

    申请日：2009-10-09

    Applicant: Scott Luning ,  Frank Scott Johnson

    Inventor： Scott Luning ,  Frank Scott Johnson

    IPC: H01L21/00 ,  H01L21/84 ,  H01L21/338 ,  H01L21/336 ,  H01L21/3205

    CPC classification number: H01L29/7842 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

    Abstract translation: 提供一种制造半导体器件的方法。 所述方法在半导体衬底上形成翅片布置，所述翅片布置包括一个或多个半导体翅片结构。 该方法通过形成覆盖鳍片布置的栅极布置继续，其中栅极布置包括一个或多个相邻栅极结构。 该方法通过在每个栅极结构的侧壁周围形成外部间隔来进行。 然后使用栅极结构和外部间隔物作为蚀刻掩模来选择性地蚀刻鳍片布置，从而导致栅极结构下面的一个或多个半导体鳍片部分。 该方法通过在一个或多个半导体鳍片部分的侧壁附近形成应力/应变诱导材料来继续。

    FINFET STRUCTURES WITH FINS HAVING STRESS-INDUCING CAPS AND METHODS FOR FABRICATING THE SAME
    20.
    发明申请
    FINFET STRUCTURES WITH FINS HAVING STRESS-INDUCING CAPS AND METHODS FOR FABRICATING THE SAME 审中-公开
    具有应力诱导颗粒的FINS的FINFET结构及其制造方法

    公开(公告)号：US20100308409A1

    公开(公告)日：2010-12-09

    申请号：US12480263

    申请日：2009-06-08

    Applicant: Frank S. Johnson ,  Scott Luning ,  Michael J. Hargrove

    Inventor： Frank S. Johnson ,  Scott Luning ,  Michael J. Hargrove

    IPC: H01L27/088 ,  H01L21/308 ,  H01L21/31 ,  H01L21/8234

    CPC classification number: H01L21/3086 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/7843

    Abstract: FinFET structures with fins having stress-inducing caps and methods for fabricating such FinFET structures are provided. In an exemplary embodiment, a method for forming stressed structures comprises forming a first stress-inducing material overlying a semiconductor material and forming spacers overlying the first stress-inducing material. The first stress-inducing material is etched using the spacers as an etch mask to form a plurality of first stress-inducing caps. The semiconductor material is etched using the plurality of first stress-inducing caps as an etch mask.

    Abstract translation: 提供具有应力诱导帽的翅片的FinFET结构和用于制造这种FinFET结构的方法。 在示例性实施例中，用于形成应力结构的方法包括形成覆盖半导体材料的第一应力诱导材料并形成覆盖第一应力诱导材料的间隔物。 使用间隔物作为蚀刻掩模蚀刻第一应力诱导材料，以形成多个第一应力诱导帽。 使用多个第一应力诱导盖作为蚀刻掩模蚀刻半导体材料。

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