公开(公告)号：US08559220B2

公开(公告)日：2013-10-15

申请号：US12952609

申请日：2010-11-23

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： G11C16/04 ,  G11C16/26 ,  G11C16/28 ,  G11C5/02 ,  G11C5/06 ,  G11C5/10 ,  G11C11/24 ,  G11C7/00 ,  G11C11/40 ,  G11C11/35 ,  G11C11/34

CPC分类号： G11C11/405 ,  G11C16/0425 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225

摘要： The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is formed on or in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

摘要翻译： 半导体器件包括第一布线; 第二布线 第三线; 第四布线 具有第一栅电极，第一源电极和第一漏电极的第一晶体管; 以及具有第二栅电极，第二源电极和第二漏电极的第二晶体管。 第一晶体管形成在包括半导体材料的衬底上或衬底中。 第二晶体管包括氧化物半导体层。

公开(公告)号：US08508967B2

公开(公告)日：2013-08-13

申请号：US13223490

申请日：2011-09-01

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C11/24

CPC分类号： G11C5/025

摘要： An object is to provide a semiconductor device having a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device is provided with both a memory circuit including a transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small) and a peripheral circuit such as a driver circuit including a transistor including a material other than an oxide semiconductor (in other words, a transistor capable of operating at sufficiently high speed). The peripheral circuit is provided in a lower portion and the memory circuit is provided in an upper portion; thus, the area and size of the semiconductor device can be decreased.

摘要翻译： 目的是提供一种具有新颖结构的半导体器件，其即使在未被供电且具有无限数量的写周期的情况下也能够保存存储的数据。 一种半导体器件具有包括包括氧化物半导体（在更广泛的意义上为截止电流足够小的晶体管）的晶体管的存储器电路以及诸如包括晶体管的驱动电路的外围电路，该晶体管包括其他材料 比氧化物半导体（换句话说，能够以足够高的速度运行的晶体管）。 外围电路设置在下部，存储电路设置在上部; 因此，可以减小半导体器件的面积和尺寸。

公开(公告)号：US08421081B2

公开(公告)日：2013-04-16

申请号：US13331645

申请日：2011-12-20

申请人： Kiyoshi Kato ,  Jun Koyama ,  Toshihiko Saito ,  Shunpei Yamazaki

发明人： Kiyoshi Kato ,  Jun Koyama ,  Toshihiko Saito ,  Shunpei Yamazaki

IPC分类号： H01L21/02

CPC分类号： H01L27/1156 ,  G11C11/404 ,  H01L27/1225

摘要： The first transistor includes first and second electrodes which are a source and a drain, and a first gate electrode overlapping with a first channel formation region with an insulating film provided therebetween. The second transistor includes third and fourth electrodes which are a source and a drain, and a second channel formation region which is provided between a second gate electrode and a third gate electrode with insulating films provided between the second channel formation region and the second gate electrode and between the second channel formation region and the third gate electrode. The first and second channel formation regions contain an oxide semiconductor, and the second electrode is connected to the second gate electrode.

摘要翻译： 第一晶体管包括作为源极和漏极的第一和第二电极，以及与第一沟道形成区域重叠的第一栅电极，其间设置有绝缘膜。 第二晶体管包括作为源极和漏极的第三和第四电极以及设置在第二栅电极和第三栅极之间的第二沟道形成区，其中设置在第二沟道形成区和第二栅电极之间的绝缘膜 并且在第二通道形成区域和第三栅电极之间。 第一和第二沟道形成区域包含氧化物半导体，并且第二电极连接到第二栅电极。

公开(公告)号：US08339836B2

公开(公告)日：2012-12-25

申请号：US12987302

申请日：2011-01-10

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： G11C11/24 ,  G11C11/22

CPC分类号： H01L27/10805 ,  G11C5/063 ,  G11C11/403 ,  G11C11/405 ,  G11C16/02 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L28/60

摘要： An object is to provide a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of times of writing operations. A semiconductor device includes a source-bit line, a first signal line, a second signal line, a word line, and a memory cell connected between the source-bit lines. The memory cell includes a first transistor, a second transistor, and a capacitor. The second transistor is formed including an oxide semiconductor material. A gate electrode of the first transistor, one of a source and drain electrodes, and one of electrodes of the capacitor are electrically connected to one another. The source-bit line and a source electrode of the first transistor are electrically connected to each other. Another source-bit line adjacent to the above source-bit line and a drain electrode of the first transistor are electrically connected to each other.

摘要翻译： 目的是提供一种具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保留存储的数据，并且对写入操作的次数没有限制。 半导体器件包括源极线，第一信号线，第二信号线，字线和连接在源极线之间的存储单元。 存储单元包括第一晶体管，第二晶体管和电容器。 形成包括氧化物半导体材料的第二晶体管。 第一晶体管的栅极，源极和漏极之一以及电容器的电极中的一个彼此电连接。 第一晶体管的源极线和源电极彼此电连接。 与上述源极线相邻的另一个源极线和第一晶体管的漏极彼此电连接。

公开(公告)号：US08289753B2

公开(公告)日：2012-10-16

申请号：US12917557

申请日：2010-11-02

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： G11C11/24

CPC分类号： G11C7/12 ,  G11C11/24 ,  G11C11/405 ,  G11C2211/4016 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1108 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225

摘要： An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring, a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode are included. The first transistor is provided over a substrate including a semiconductor material and a second transistor includes an oxide semiconductor layer.

摘要翻译： 目的在于提供一种具有新颖结构的半导体器件。 第一个接线 第二布线 第三布线，第四布线; 第一晶体管，包括第一栅极电极，第一源极电极和第一漏极电极; 包括第二晶体管，包括第二栅电极，第二源电极和第二漏电极。 第一晶体管设置在包括半导体材料的衬底上，并且第二晶体管包括氧化物半导体层。

公开(公告)号：US20110156027A1

公开(公告)日：2011-06-30

申请号：US12976564

申请日：2010-12-22

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H01L27/108 ,  H01L29/12

CPC分类号： H01L27/1052 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/79 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78696

摘要： An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

摘要翻译： 本发明的一个实施例的目的是提供一种具有新颖结构的半导体器件，其中即使在数据存储时间中没有提供电力的情况下也可以存储存储的数据，并且对写入次数没有限制。 半导体器件包括：第一晶体管，其包括使用除了氧化物半导体之外的半导体材料的第一沟道形成区域;第二晶体管，其包括使用氧化物半导体材料的第二沟道形成区域;以及电容器。 第二晶体管的第二源电极和第二漏电极之一电连接到电容器的一个电极。

公开(公告)号：US20110121285A1

公开(公告)日：2011-05-26

申请号：US12949631

申请日：2010-11-18

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H01L29/12

CPC分类号： H01L27/1203 ,  G11C11/403 ,  G11C11/405 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/1225

摘要： It is an object to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, and a second transistor including a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided over a substrate including a semiconductor material, and the second transistor includes an oxide semiconductor layer.

摘要翻译： 本发明的目的是提供一种具有新颖结构的半导体器件。 半导体器件包括第一布线，第二布线，第三布线，第四布线，包括第一栅电极，第一源电极和第一漏电极的第一晶体管，以及包括第二栅电极的第二晶体管， 第二源电极和第二漏电极。 第一晶体管设置在包括半导体材料的衬底上，并且第二晶体管包括氧化物半导体层。

公开(公告)号：US20110110145A1

公开(公告)日：2011-05-12

申请号：US12917557

申请日：2010-11-02

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： G11C11/40

CPC分类号： G11C7/12 ,  G11C11/24 ,  G11C11/405 ,  G11C2211/4016 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1108 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225

摘要： An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring, a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode are included. The first transistor is provided over a substrate including a semiconductor material and a second transistor includes an oxide semiconductor layer.

摘要翻译： 目的在于提供一种具有新颖结构的半导体器件。 第一个接线 第二布线 第三布线，第四布线; 第一晶体管，包括第一栅极电极，第一源极电极和第一漏极电极; 包括第二晶体管，包括第二栅电极，第二源电极和第二漏电极。 第一晶体管设置在包括半导体材料的衬底上，并且第二晶体管包括氧化物半导体层。

公开(公告)号：US06885059B2

公开(公告)日：2005-04-26

申请号：US10725535

申请日：2003-12-03

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H01L21/336 ,  H01L21/77 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788

CPC分类号： H01L27/1214 ,  H01L27/1203 ,  H01L29/66757 ,  H01L29/78654 ,  H01L29/78675 ,  H01L29/78696

摘要： A nonvolatile memory transistor with multi values being capable of suppressing a short channel effect is provided. In an active region of a memory transistor, stripe-shaped impurity regions (pinning regions) are formed in a channel length direction. The pinning regions suppress the spread of a depletion layer of a drain region, and a short channel effect caused by fine processing. Furthermore, in a memory transistor using pinning regions, by assigning one value or one bit of data to each channel forming region, the memory transistor is allowed to have multi values. More specifically, the present invention has a configuration in which a floating gate electrode is provided on each of a plurality of channel forming regions via a first gate insulating film, and an electric potential can be applied independently to a plurality of pinning regions.

摘要翻译： 提供了具有能够抑制短通道效应的具有多个值的非易失性存储晶体管。 在存储晶体管的有源区中，沿通道长度方向形成条状杂质区（钉扎区）。 钉扎区域抑制漏极区域的耗尽层的扩散以及由精细加工引起的短沟道效应。 此外，在使用钉扎区域的存储器晶体管中，通过向每个沟道形成区域分配一个或多个数据位，允许存储晶体管具有多个值。 更具体地说，本发明具有通过第一栅极绝缘膜在多个沟道形成区域中的每一个上设置浮置栅电极的结构，并且可以独立地对多个钉扎区域施加电位。

公开(公告)号：US09613964B2

公开(公告)日：2017-04-04

申请号：US13034278

申请日：2011-02-24

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H01L27/108 ,  H01L27/105 ,  G11C11/24 ,  H01L27/1156 ,  H01L27/12 ,  H01L49/02

CPC分类号： H01L27/105 ,  G11C11/24 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

摘要： A semiconductor device including a non-volatile memory cell including a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor is provided. Data is written or rewritten to the memory cell by turning on the writing transistor and supplying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor so that the predetermined amount of charge is held in the node. Further, when a transistor whose threshold voltage is controlled and set to a positive voltage is used as the reading transistor, a reading potential is a positive potential.