公开(公告)号：US20200342938A1

公开(公告)日：2020-10-29

申请号：US16503355

申请日：2019-07-03

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  THUAN VU ,  STANLEY HONG ,  STEPHEN TRINH ,  ANH LY ,  HAN TRAN ,  KHA NGUYEN ,  HIEN PHAM

IPC: G11C11/56 ,  G11C11/16 ,  G11C11/4074 ,  G06F17/16 ,  G06N3/06

Abstract: Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.

公开(公告)号：US20240338144A1

公开(公告)日：2024-10-10

申请号：US18212066

申请日：2023-06-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEPHEN TRINH ,  HOA VU ,  STANLEY HONG ,  THUAN VU

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/062 ,  G06F3/0679 ,  G11C16/08

Abstract: Numerous examples are disclosed of a masking circuit for inputs and outputs in a neural network array. In one example, a system comprises a neural network array comprising a plurality of non-volatile memory cells arranged into rows and columns; and row circuits for respective rows in the neural network array, the row circuits comprising a masking circuit to prevent an application of a sparse input to one or more rows in the array when a condition is satisfied.

公开(公告)号：US20240112003A1

公开(公告)日：2024-04-04

申请号：US18077993

申请日：2022-12-08

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  STEPHEN TRINH ,  STANLEY HONG ,  THUAN VU ,  NGHIA LE ,  HIEN PHAM

IPC: G06N3/063 ,  G06F5/01 ,  G06F7/501

CPC classification number: G06N3/063 ,  G06F5/01 ,  G06F7/501

Abstract: Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.

公开(公告)号：US20230325650A1

公开(公告)日：2023-10-12

申请号：US17847491

申请日：2022-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  THUAN VU ,  STANLEY HONG ,  STEPHEN TRINH ,  MARK REITEN

IPC: G06G7/06 ,  G06G7/16

CPC classification number: G06G7/06 ,  G06G7/16

Abstract: Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog outputs. In one example, a system comprises a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns; and an output circuit to receive a respective neuron current from respective columns of the vector by matrix multiplication array and to generate a respective output voltage, the output circuit comprising a neuron scalar to generate a scaled current from the received respective neuron current, and a current-to-voltage converter to convert the scaled current into the respective output voltage.

公开(公告)号：US20210358551A1

公开(公告)日：2021-11-18

申请号：US17082956

申请日：2020-10-28

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  STANLEY HONG ,  STEPHEN TRINH ,  THUAN VU ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G11C11/56 ,  G06N3/063

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using a tuning mechanism. This achieves extreme programming accuracy and programming speed.

公开(公告)号：US20210295907A1

公开(公告)日：2021-09-23

申请号：US17024410

申请日：2020-09-17

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  THUAN VU ,  STEPHEN TRINH ,  STANLEY HONG ,  ANH LY ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G06N3/063

Abstract: Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. High voltage circuits used to generate high voltages applied to terminals of the non-volatile memory cells during the precision tuning process are also disclosed. Programming sequences for the application of the voltages to the terminals to minimize the occurrence of disturbances during tuning are also disclosed.

公开(公告)号：US20210280240A1

公开(公告)日：2021-09-09

申请号：US16987101

申请日：2020-08-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan VU ,  STEPHEN TRINH ,  STANLEY HONG ,  ANH LY ,  VIPIN Tiwari

IPC: G11C11/54 ,  G11C16/28 ,  G11C16/04 ,  H03F3/00 ,  H03M1/16 ,  H03M1/38 ,  G06N3/063

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)−(W−). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W− values.

公开(公告)号：US20210257023A1

公开(公告)日：2021-08-19

申请号：US17199243

申请日：2021-03-11

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  ANH LY ,  THUAN VU ,  STANLEY HONG ,  FENG ZHOU ,  XIAN LIU ,  NHAN DO

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C7/06

Abstract: Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed. In one embodiment, a set-while-verify circuit for performing a set operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the set operation is complete. In another embodiment, a reset-while-verify circuit for performing a reset operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the reset operation is complete.

公开(公告)号：US20200349421A1

公开(公告)日：2020-11-05

申请号：US16449201

申请日：2019-06-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEPHEN TRINH ,  THUAN VU ,  STANLEY HONG ,  VIPIN TIWARI ,  MARK REITEN ,  NHAN DO

IPC: G06N3/063 ,  G11C16/04 ,  G11C11/54 ,  G06F17/16

Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.