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    Semiconductor package and fabrication method thereof
    12.
    发明授权
    Semiconductor package and fabrication method thereof 有权
    半导体封装及其制造方法

    公开(公告)号：US08829687B2

    公开(公告)日：2014-09-09

    申请号：US13722138

    申请日：2012-12-20

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Mu-Hsuan Chan ,  Wan-Ting Chen ,  Yi-Chian Liao ,  Chun-Tang Lin ,  Yi-Chi Lai

    IPC: H01L23/48 ,  H01L21/00 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498

    CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L21/78 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

    Abstract: A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.

    Abstract translation: 提供一种半导体封装，其包括：具有相反的第一和第二表面的半导体衬底; 形成在所述半导体衬底的第一表面上的粘合剂层; 至少设置在所述粘合剂层上的半导体芯片; 形成在用于封装半导体芯片的粘合剂层上的密封剂; 以及贯穿半导体衬底的第一和第二表面和粘合剂层并且电连接到半导体芯片的多个导电柱，从而有效地降低了制造成本，缩短了制造时间并提高了产品的可靠性。

    SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
    13.
    发明申请
    SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF 有权
    半导体封装及其制造方法

    公开(公告)号：US20140084484A1

    公开(公告)日：2014-03-27

    申请号：US13922828

    申请日：2013-06-20

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Mu-Hsuan Chan ,  Wan-Ting Chen ,  Chun-Tang Lin ,  Yi-Che Lai

    IPC: H01L23/00

    CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/351 ,  H01L2924/00

    Abstract: A semiconductor package is provided, which includes: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top surface of the interposer; a redistribution layer formed on the encapsulant and the top surface of the interposer; and at least a semiconductor element disposed on the redistribution layer. The top surface of the interposer is flush with a surface of the encapsulant so as for the redistribution layer to have a planar surface for disposing the semiconductor element, thereby preventing warpage of the interposer and improving the reliability of electrical connection between the redistribution layer and the semiconductor element.

    Abstract translation: 提供一种半导体封装，其包括：载体; 至少设置在所述载体上的插入件; 形成在所述载体上的密封剂，用于在暴露所述插入件的顶表面的同时封装所述插入件; 在所述密封剂和所述插入件的顶表面上形成的再分布层; 以及设置在再分布层上的至少一个半导体元件。 插入器的顶表面与密封剂的表面齐平，以使再分布层具有用于设置半导体元件的平坦表面，从而防止插入件的翘曲，并提高再分布层与第二层之间的电连接的可靠性 半导体元件。

    SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
    14.
    发明申请
    SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF 有权
    半导体封装及其制造方法

    公开(公告)号：US20140084455A1

    公开(公告)日：2014-03-27

    申请号：US13722138

    申请日：2012-12-20

    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

    Inventor： Mu-Hsuan Chan ,  Wan-Ting Chen ,  Yi-Chian Liao ,  Chun-Tang Lin ,  Yi-Chi Lai

    IPC: H01L23/498 ,  H01L21/78

    CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L21/78 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

    Abstract: A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.

    Abstract translation: 提供一种半导体封装，其包括：具有相反的第一和第二表面的半导体衬底; 形成在所述半导体衬底的第一表面上的粘合剂层; 至少设置在所述粘合剂层上的半导体芯片; 形成在用于封装半导体芯片的粘合剂层上的密封剂; 以及贯穿半导体衬底的第一和第二表面和粘合剂层并且电连接到半导体芯片的多个导电柱，从而有效地降低了制造成本，缩短了制造时间并提高了产品的可靠性。

    Fabrication method of electronic package
    15.
    发明授权
    Fabrication method of electronic package 有权

    公开(公告)号：US10403567B2

    公开(公告)日：2019-09-03

    申请号：US15866144

    申请日：2018-01-09

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi

    IPC: H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56

    Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

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