公开(公告)号：US06746971B1

公开(公告)日：2004-06-08

申请号：US10314060

申请日：2002-12-05

申请人： Minh Van Ngo ,  Sergey D. Lopatin ,  Suzette K. Pangrle ,  Nicholas H. Tripsas ,  Hieu T. Pham

发明人： Minh Van Ngo ,  Sergey D. Lopatin ,  Suzette K. Pangrle ,  Nicholas H. Tripsas ,  Hieu T. Pham

IPC分类号： H01L2131

CPC分类号： H01L51/0036 ,  B82Y10/00 ,  G11C13/0009 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/025 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/28 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0038 ,  H01L51/0041 ,  H01L51/005 ,  H01L51/0053 ,  H01L51/0059 ,  H01L51/0077 ,  H01L51/0081 ,  H01L51/0084 ,  H01L51/0085

摘要： An organic memory cell made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The controllably conductive media changes its impedance when an external stimuli such as an applied electric field is imposed thereon. Methods of making the organic memory devices/cells, methods of using the organic memory devices/cells, and devices such as computers containing the organic memory devices/cells are also disclosed.

摘要翻译： 公开了一种由在两个电极之间具有可控导电介质的两个电极制成的有机存储单元。 可控导电介质包含有机半导体层和无源层。 当施加外部刺激（例如施加的电场）时，可控导电介质改变其阻抗。 还公开了制造有机存储器件/单元的方法，使用有机存储器件/单元的方法，以及诸如包含有机存储器件/单元的计算机的器件。

公开(公告)号：US06630383B1

公开(公告)日：2003-10-07

申请号：US10274063

申请日：2002-10-17

申请人： Effiong Ibok ,  Wei Zheng ,  Nicholas H. Tripsas ,  Mark T. Ramsbey ,  Fred T K Cheung

发明人： Effiong Ibok ,  Wei Zheng ,  Nicholas H. Tripsas ,  Mark T. Ramsbey ,  Fred T K Cheung

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/511

摘要： In one embodiment, a method of making a gate stack semiconductor device is disclosed. The method comprises the steps of: forming a tunnel oxide layer over a p-type semiconductor substrate; forming a floating gate over the tunnel oxide layer by first forming an n-type polysilicon layer and subjecting the n-type polysilicon layer to nitridation, and then forming a p-type polysilicon layer over the nitridated n-type polysilicon layer; and forming a high-K insulating layer over the p-type polysilicon layer.

摘要翻译： 在一个实施例中，公开了制造栅叠层半导体器件的方法。 该方法包括以下步骤：在p型半导体衬底上形成隧道氧化物层; 通过首先形成n型多晶硅层并对n型多晶硅层进行氮化，然后在氮化的n型多晶硅层上形成p型多晶硅层，在隧道氧化物层上形成浮栅; 以及在p型多晶硅层上形成高K绝缘层。

公开(公告)号：US06548855B1

公开(公告)日：2003-04-15

申请号：US10147622

申请日：2002-05-16

申请人： Mark T. Ramsbey ,  Arvind Halliyal ,  Kuo-Tung Chang ,  Nicholas H. Tripsas ,  Wei Zheng ,  Unsoon Kim

发明人： Mark T. Ramsbey ,  Arvind Halliyal ,  Kuo-Tung Chang ,  Nicholas H. Tripsas ,  Wei Zheng ,  Unsoon Kim

IPC分类号： H01L2976

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11539

摘要： A non-volatile memory device for retention of data when electrical power is terminated. The non-volatile memory device includes at least one memory cell and a charge pump for stepping up the incoming voltage supply. The charge pump includes at least one capacitor, wherein the dielectric of the charge pump capacitor and the dielectric of the memory cell are formed during the same processing step.

摘要翻译： 一种用于在电力终止时保留数据的非易失性存储器件。 非易失性存储器件包括至少一个存储单元和用于加速输入电压源的电荷泵。 电荷泵包括至少一个电容器，其中电荷泵电容器的电介质和存储单元的电介质在相同的处理步骤期间形成。

公开(公告)号：US6025240A

公开(公告)日：2000-02-15

申请号：US993600

申请日：1997-12-18

申请人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

发明人： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

公开(公告)号：US07670936B1

公开(公告)日：2010-03-02

申请号：US10273184

申请日：2002-10-18

申请人： Arvind Halliyal ,  Nicholas H. Tripsas ,  Mark T. Ramsbey

发明人： Arvind Halliyal ,  Nicholas H. Tripsas ,  Mark T. Ramsbey

IPC分类号： H01L21/425

CPC分类号： H01L21/268 ,  H01L21/02057 ,  H01L21/28202 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device includes forming an interface layer, a nitrided gate dielectric, a gate electrode, and source drain regions. The interface layer is formed in a substrate by laser processing. The nitrided gate dielectric is formed over the interface layer by laser processing. The gate electrode is formed over the substrate and the gate dielectric after the laser processing step, and source/drain regions are formed in the substrate proximate to the gate electrode.

摘要翻译： 制造半导体器件的方法包括形成界面层，氮化栅极电介质，栅电极和源漏区。 界面层通过激光加工形成在基板中。 通过激光加工在界面层上形成氮化栅极电介质。 在激光加工步骤之后，栅极电极形成在衬底和栅极电介质上，并且源极/漏极区域形成在靠近栅电极的衬底中。

公开(公告)号：US06861307B2

公开(公告)日：2005-03-01

申请号：US10631199

申请日：2003-07-31

申请人： Wei Zheng ,  Mark W. Randolph ,  Nicholas H. Tripsas ,  Zoran Krivokapic ,  Jack F. Thomas ,  Mark T. Ramsbey

发明人： Wei Zheng ,  Mark W. Randolph ,  Nicholas H. Tripsas ,  Zoran Krivokapic ,  Jack F. Thomas ,  Mark T. Ramsbey

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/792 ,  H01L21/8238

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L21/28282 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7923

摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

摘要翻译： 在硅衬底上制造双位电介质存储单元结构的方法包括在衬底内埋入掩埋位线，并在掩埋位线之间的衬底表面上制造分层岛。 该岛具有限定栅极区域的周边，并且包括在绝缘体上硅晶片的表面上的隧道介电层，在隧道介电层的表面上的隔离阻挡介电层，隔离表面上的顶部介电层 势垒介电层，以及在顶部介电层的表面上的多晶硅栅极。 去除隔离势垒介电层的一部分以在栅极区内形成底切区域，并且电荷俘获材料沉积在底切区域内。

公开(公告)号：US06787458B1

公开(公告)日：2004-09-07

申请号：US10614397

申请日：2003-07-07

申请人： Nicholas H. Tripsas ,  Matthew S. Buynoski ,  Suzette K. Pangrle ,  Uzodinma Okoroanyanwu ,  Angela T. Hui ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Ashok M. Khathuria ,  Mark S. Chang ,  Patrick K. Cheung ,  Jane V. Oglesby

发明人： Nicholas H. Tripsas ,  Matthew S. Buynoski ,  Suzette K. Pangrle ,  Uzodinma Okoroanyanwu ,  Angela T. Hui ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Ashok M. Khathuria ,  Mark S. Chang ,  Patrick K. Cheung ,  Jane V. Oglesby

IPC分类号： H01L2144

CPC分类号： H01L27/285 ,  H01L2924/0002 ,  H01L2924/00

摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.

摘要翻译： 本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。 该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔 露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

公开(公告)号：US06753570B1

公开(公告)日：2004-06-22

申请号：US10223920

申请日：2002-08-20

申请人： Nicholas H. Tripsas ,  Kuo-Tung Chang ,  Mark T. Ramsbey

发明人： Nicholas H. Tripsas ,  Kuo-Tung Chang ,  Mark T. Ramsbey

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A non-volatile memory device includes insulators between floating gates. The insulators each include both a lower trench-fill insulator portion in a trench in the substrate, and an upper protruding portion that protrudes from the substrate. Floating gates extend between the protruding portions of adjacent insulators, and are in contact with the protruding portions of the adjacent insulators. An interpoly dielectric overlies the floating gates, and a control gate overlies the interpoly dielectric. The insulators and the floating gates may make a substantially planar surface for the interpoly dielectric, which may themselves be planar.

摘要翻译： 非易失性存储器件包括浮置栅极之间的绝缘体。 绝缘体各自包括衬底中的沟槽中的下沟槽填充绝缘体部分和从衬底突出的上突出部分。 浮栅在相邻绝缘体的突出部分之间延伸，并与相邻绝缘体的突出部分接触。 互补电介质覆盖浮置栅极，并且控制栅极覆盖在多晶硅间电介质上。 绝缘体和浮动栅极可以形成用于互聚电介质的基本平坦的表面，其可以是平面的。

公开(公告)号：US06627945B1

公开(公告)日：2003-09-30

申请号：US10189651

申请日：2002-07-03

申请人： Nicholas H. Tripsas ,  Mark T. Ramsbey

发明人： Nicholas H. Tripsas ,  Mark T. Ramsbey

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/51 ,  H01L29/7883

摘要： A non-volatile memory device includes a number of memory cells, parts of which are delineated by insulators. The insulators each include both a lower trench-fill insulator portion in a trench in the substrate, and an upper protruding portion that protrudes from the substrate. Between each pair of adjacent protruding insulator portions there is a pair of floating gates, the floating gates in contact with respective of the protruding insulator portions. There is a space or gap between the floating gates, such that a portion of a control gate enters therein, separated from the substrate by only an interpoly dielectric such as an oxide-nitride-oxide (ONO) stack, and a tunnel oxide. By storing charge on the floating gates, the conductivity of a channel between the floating gates may be altered. For example, conductivity through the channel may be “pinched off” by storing charge on the floating gates.

摘要翻译： 非易失性存储器件包括多个存储器单元，其中的一部分由绝缘体表示。 绝缘体各自包括衬底中的沟槽中的下沟槽填充绝缘体部分和从衬底突出的上突出部分。 在每对相邻的突出绝缘体部分之间存在一对浮动栅极，浮动栅极与相应的突出的绝缘体部分接触。 在浮动栅极之间存在空隙或间隙，使得控制栅极的一部分进入其中，仅通过诸如氧化物 - 氧化物 - 氧化物（ONO）堆叠的多层电介质和隧道氧化物与衬底分离。 通过在浮动栅极上存储电荷，可以改变浮置栅极之间的通道的电导率。 例如，通过在浮动栅极上存储电荷可以通过沟道的导电性被“夹断”。

公开(公告)号：US6110833A

公开(公告)日：2000-08-29

申请号：US33836

申请日：1998-03-03

申请人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan

发明人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan

IPC分类号： A61K38/00 ,  A61K38/30 ,  H01L21/8247 ,  H01L21/70

CPC分类号： H01L27/11521 ,  A61K38/30

摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.

摘要翻译： 提供了一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层。 然后，形成用于掩蔽多晶硅层的牺牲氧化物层和氮化物层。 蚀刻掩模层的至少一部分以对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。 多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极分开。 绝缘体被蚀刻以形成在第一存储单元的浮动栅极和第二存储单元的浮置栅极之间具有逐渐倾斜的侧壁的间隙，将第一存储单元的浮置栅极与第一存储单元的浮动栅极隔离的间隙 第二存储单元。 此后，形成基本上不具有台阶高度突然变化的互聚电介质层和第二多晶硅（poly II）层。