公开(公告)号：US5764076A

公开(公告)日：1998-06-09

申请号：US670472

申请日：1996-06-26

申请人： Napoleon W. Lee ,  Derek R. Curd ,  Jeffrey H. Seltzer ,  Jeffrey Goldberg ,  David Chiang ,  Kameswara K. Rao ,  Nicholas Kucharewski, Jr.

发明人： Napoleon W. Lee ,  Derek R. Curd ,  Jeffrey H. Seltzer ,  Jeffrey Goldberg ,  David Chiang ,  Kameswara K. Rao ,  Nicholas Kucharewski, Jr.

IPC分类号： G06F17/50 ,  H03K19/177

CPC分类号： H03K19/17752 ,  G06F17/5054 ,  H03K19/17704 ,  H03K19/17756

摘要： A complex programmable logic device (PLD) that includes a number of programmable function blocks and an instruction bus for receiving programming instructions. The programming instructions are used to program the function blocks to enable the PLD to perform one or more desired logic functions. The PLD also includes an instruction-blocking circuit that is connected to each of the functional blocks. When directed by a user, the instruction blocking circuit selectively blocks programming instructions on the instruction bus from one or more of the function blocks while allowing the other function blocks to receive the programming instructions. Thus, one or more function blocks in the PLD are reprogrammed without interrupting the operation of the remaining function blocks.

摘要翻译： 一种复杂的可编程逻辑器件（PLD），包括多个可编程功能块和用于接收编程指令的指令总线。 编程指令用于对功能块进行编程，以使PLD能够执行一个或多个所需的逻辑功能。 PLD还包括连接到每个功能块的指令阻塞电路。 当用户指示时，指令分块电路有选择地阻止来自一个或多个功能块的指令总线上的编程指令，同时允许其他功能块接收编程指令。 因此，PLD中的一个或多个功能块被重新编程，而不中断剩余功能块的操作。

公开(公告)号：US5563827A

公开(公告)日：1996-10-08

申请号：US533412

申请日：1995-09-25

申请人： Napoleon W. Lee ,  Derek R. Curd ,  Wei-Yi Ku ,  Sholeh Diba ,  George Simmons

发明人： Napoleon W. Lee ,  Derek R. Curd ,  Wei-Yi Ku ,  Sholeh Diba ,  George Simmons

IPC分类号： G11C16/12 ,  G11C13/00

CPC分类号： G11C16/12

摘要： A wordline driver for a wordline in an integrated programmable logic device (PLD) having flash memory cells. The wordline driver includes an input terminal that accepts a binary wordline input signal, a pass gate coupled to the input terminal and to a mode-control terminal, and an inverter that receives an input from the pass gate or the mode-control terminal, depending on the operating mode of the PLD. The output signal from the inverter is coupled to a multiplexer that selects between that output and a signal from a voltage supply, the signal selected depending on the operating mode of the PLD. The multiplexer outputs the selected signal to the wordline of the PLD.

摘要翻译： 具有闪存单元的集成可编程逻辑器件（PLD）中的字线的字线驱动器。 字线驱动器包括接受二进制字线输入信号的输入端子，耦合到输入端子和模式控制端子的通过栅极，以及根据通路或模式控制端子接收输入的反相器， 在PLD的操作模式下。 来自反相器的输出信号被耦合到多路复用器，该多路复用器在该输出和来自电压源的信号之间选择根据PLD的操作模式选择的信号。 复用器将所选信号输出到PLD的字线。

公开(公告)号：US07227378B2

公开(公告)日：2007-06-05

申请号：US11100971

申请日：2005-04-07

申请人： Brandon J. Blodget ,  Scott P. McMillan ,  Philip B. James-Roxby ,  Prasanna Sundararajan ,  Eric R. Keller ,  Derek R. Curd ,  Punit S. Kalra ,  Richard J. LeBlanc ,  Vincent P. Eck

发明人： Brandon J. Blodget ,  Scott P. McMillan ,  Philip B. James-Roxby ,  Prasanna Sundararajan ,  Eric R. Keller ,  Derek R. Curd ,  Punit S. Kalra ,  Richard J. LeBlanc ,  Vincent P. Eck

IPC分类号： G06F7/38

CPC分类号： H03K19/17752 ,  G06F15/7867 ,  H03K19/17732 ,  H03K19/17756

摘要： A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.

摘要翻译： 一种部分重新配置具有可编程模块的IC的方法，包括从配置存储器阵列读取配置信息的帧的步骤; 修改所述配置信息的至少一部分，从而创建修改的配置信息帧; 并用修改的帧覆盖配置存储器阵列中的配置信息的现有帧，由此部分地重新配置IC。

公开(公告)号：US06314539B1

公开(公告)日：2001-11-06

申请号：US09176659

申请日：1998-10-21

申请人： Neil G. Jacobson ,  Derek R. Curd

发明人： Neil G. Jacobson ,  Derek R. Curd

IPC分类号： G01R3128

CPC分类号： G01R31/318541

摘要： A Boundary-Scan register (BSR) cell including a bypass circuit for selectively routing data signals around the data shift register of the BSR cell so that the BSR cell can be effectively removed from a BSR chain during Boundary-Scan Test procedures involving IEEE Standard 1149.1 compliant integrated circuits. In one embodiment, the BSR cell includes a bypass MUX having a first input terminal connected to a test data input (TDI) terminal of the BSR cell, a second input terminal connected to an output terminal of the shift register, and an output terminal connected to the test data output (TDO) terminal. The BSR cell operates in a “normal” mode (i.e., included in the BSR chain) when the bypass MUX is controlled to pass data signals output from the shift register to the TDO terminal. In contrast, the BSR cell is selectively bypassed (i.e., removed from the BSR chain) when the bypass MUX is controlled to pass the TDI signal to the TDO terminal. The BSR cell also includes mode control MUX having a first input terminal connected to receive a MODE signal generated by a Boundary-Scan TAP controller, a second input terminal connected to an OFF (disable) signal source, and an output terminal connected to the output MUX of the BSR cell. When the BSR cell operates in the “normal”, the mode control MUX is controlled to pass the MODE signal to the output MUX. In contrast, when the BSR cell is selectively bypassed, the OFF signal is passed to the output MUX.

摘要翻译： 一种边界扫描寄存器（BSR）单元，包括用于选择性地在BSR单元的数据移位寄存器周围数据信号路由的旁路电路，使得可以在涉及IEEE标准1149.1的边界扫描测试程序期间将BSR单元有效地从BSR链中移除 兼容的集成电路。 在一个实施例中，BSR单元包括旁路MUX，其具有连接到BSR单元的测试数据输入（TDI）端的第一输入端，连接到移位寄存器的输出端的第二输入端和连接的输出端 到测试数据输出（TDO）端子。 当旁路MUX被控制以将从移位寄存器输出的数据信号传递到TDO终端时，BSR单元工作在“正常”模式（即包括在BSR链中）。 相反，当旁路MUX被控制以将TDI信号传递到TDO终端时，BSR单元被选择性地旁路（即从BSR链移除）。 BSR单元还包括模式控制MUX，其具有被连接以接收由边界扫描TAP控制器产生的MODE信号的第一输入端子，连接到OFF（禁止）信号源的第二输入端子以及连接到输出端的输出端子 BSR单元的MUX。 当BSR单元工作在“正常”时，控制模式控制MUX将MODE信号传递到输出MUX。 相反，当选择性地旁路BSR单元时，OFF信号被传递到输出MUX。

公开(公告)号：US5949987A

公开(公告)日：1999-09-07

申请号：US48923

申请日：1998-03-26

申请人： Derek R. Curd ,  Kameswara K. Rao ,  Napoleon W. Lee

发明人： Derek R. Curd ,  Kameswara K. Rao ,  Napoleon W. Lee

IPC分类号： H03K19/173 ,  G01R31/3185 ,  G06F17/50 ,  H03K19/177 ,  G05B19/045

CPC分类号： H03K19/1776 ,  G01R31/318516 ,  G06F17/5054 ,  H03K19/17704

摘要： An in-system programming/erasing/verifying structure for non-volatile programmable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e. result), of the ISP operations to either the end-user or the supporting software.

摘要翻译： 用于非易失性可编程逻辑器件的系统内编程/擦除/验证结构包括数据输入引脚，数据输出引脚，指令寄存器，包括ISP寄存器的多个数据寄存器，其中所述指令寄存器和所述多个 数据寄存器并联在所述数据输入引脚和所述数据输出引脚之间，以及用于使所述指令寄存器和所述多个数据寄存器同步的控制器。 ISP寄存器包括：地址字段，数据字段和状态字段。 ISP指令只需输入一次即可对整个设备进行编程/擦除。 具体来说，与已知的ISP方法相比，地址/数据分组可以在数据输入引脚的每个数据包之间插入多个指令，从而大大减少编程/擦除整个器件所需的时间，而将ISP / 此外，本发明提供了一种用于向最终用户或支持软件提供ISP操作的状态（即结果）的有效方法。

公开(公告)号：US5838901A

公开(公告)日：1998-11-17

申请号：US692389

申请日：1996-08-05

申请人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

发明人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

IPC分类号： G06F12/14 ,  G06F21/00 ,  G06F1/00

CPC分类号： G06F21/76 ,  G06F12/1466

摘要： An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

公开(公告)号：US5661685A

公开(公告)日：1997-08-26

申请号：US533131

申请日：1995-09-25

申请人： Napoleon W. Lee ,  Derek R. Curd ,  Sholeh Diba ,  Prasad Sastry ,  Mihai G. Statovici ,  Kameswara K. Rao

发明人： Napoleon W. Lee ,  Derek R. Curd ,  Sholeh Diba ,  Prasad Sastry ,  Mihai G. Statovici ,  Kameswara K. Rao

IPC分类号： G11C16/02 ,  G06F17/50 ,  H03K19/177 ,  G11C7/00

CPC分类号： H03K19/17784 ,  G06F17/5054 ,  H03K19/17704

摘要： An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.

摘要翻译： 集成可编程逻辑器件（PLD）包括闪存EPROM存储晶体管。 PLD包括多路复用器，其选择性地向存储晶体管提供编程，擦除或验证电压。 可以使用外部电源提供程序，擦除和验证电压，或者可以由片上电荷泵发生器内部产生。 PLD上的可配置存储器用于调整每个片上电荷泵发生器的输出电压。

公开(公告)号：US5650672A

公开(公告)日：1997-07-22

申请号：US533413

申请日：1995-09-25

申请人： Derek R. Curd

发明人： Derek R. Curd

IPC分类号： H03K17/0416 ,  H03K17/693 ,  H01H35/00

CPC分类号： H03K17/04163 ,  H03K17/693 ,  Y10T307/50 ,  Y10T307/647 ,  Y10T307/675 ,  Y10T307/696 ,  Y10T307/702 ,  Y10T307/724 ,  Y10T307/729 ,  Y10T307/858

摘要： A multiplexor having a multiplexor control input terminal for selectively providing one of a plurality of conductor voltage levels to a conductor. The multiplexor includes a first switch, which is coupled to the conductor, for providing a first conductor voltage level to the conductor. A second switch is also included and coupled to the conductor for providing a second conductor voltage level to the conductor. To provide a selective discharge path for the conductor during switching, the multiplexor further includes a third switch coupled to the conductor. A discharge circuit is also provided and coupled to the conductor and the third switch for sensing the voltage level of the conductor to turn on the third switch as necessary at the early stage of switching among conductor voltage levels.

摘要翻译： 一种具有多路复用器控制输入端的复用器，用于选择性地向导体提供多个导体电压电平中的一个。 多路复用器包括耦合到导体的第一开关，用于向导体提供第一导体电压电平。 还包括第二开关并耦合到导体，以向导体提供第二导体电压电平。 为了在切换期间为导体提供选择性放电路径，多路复用器还包括耦合到导体的第三开关。 还提供放电电路并耦合到导体和第三开关，用于感测导体的电压电平，以在导体电压电平之间的切换的早期阶段根据需要接通第三开关。

公开(公告)号：US07143329B1

公开(公告)日：2006-11-28

申请号：US10796475

申请日：2004-03-09

申请人： Stephen M. Trimberger ,  Austin H. Lesea ,  Derek R. Curd

发明人： Stephen M. Trimberger ,  Austin H. Lesea ,  Derek R. Curd

IPC分类号： G06F11/00 ,  G06F11/30 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00

CPC分类号： G01R31/318519 ,  G06F11/1044 ,  G11C7/1006 ,  G11C2029/0411 ,  H03K19/17764

摘要： A system and method are disclosed for error correction in a programmable logic device (PLD). A frame circuit retrieves data from each column of configuration memory of the PLD, and a check memory stores of a plurality of check words. A buffer circuit is coupled to the check memory and to the frame circuit. The buffer circuit assembles blocks of data from data retrieved by the frame circuit and from corresponding check words in the check memory. A plurality of storage elements are provided for storage of status information. A check circuit is coupled to the storage elements and to the buffer circuit. Each block is checked by the check circuit using an error correcting code, and data indicating detected errors is stored in the storage elements.

摘要翻译： 公开了用于可编程逻辑器件（PLD）中的纠错的系统和方法。 帧电路从PLD的配置存储器的每列检索数据，并且检查存储器存储多个检查字。 缓冲电路耦合到校验存储器和帧电路。 缓冲电路从由帧电路检索的数据和从检查存储器中的对应检查词组装数据块。 提供多个存储元件用于存储状态信息。 检查电路耦合到存储元件和缓冲电路。 通过校验电路使用错误校正码检查每个块，并且将指示检测到的错误的数据存储在存储元件中。

公开(公告)号：US06353333B1

公开(公告)日：2002-03-05

申请号：US09595780

申请日：2000-06-16

申请人： Derek R. Curd ,  Hy V. Nguyen

发明人： Derek R. Curd ,  Hy V. Nguyen

IPC分类号： H03K190185

CPC分类号： H03K19/00315

摘要： A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. The interface circuit includes an impedance control circuit, an output buffer, an input buffer, an isolation circuit, and a pullup protection circuit. The output buffer includes a pullup transistor and a pulldown transistor for applying an output signal to an I/O pad. When a high voltage (i.e., higher than the internal voltage of the interface circuit) is applied to the I/O pad, the pullup protection circuit drives the gate of the pullup transistor to the high I/O pad voltage to ensure that no current flows to the positive supply voltage. Also, the isolation circuit couples the high I/O pad voltage to the body (well) of the pullup transistor to prevent leakage current through parasitic diodes formed by the pullup transistor.

摘要翻译： 具有高电压公差的低压接口电路使得具有不同电源电平的器件能够有效耦合在一起，而不会有明显的漏电流或电路损坏。 接口电路包括阻抗控制电路，输出缓冲器，输入缓冲器，隔离电路和上拉保护电路。 输出缓冲器包括用于将输出信号施加到I / O焊盘的上拉晶体管和下拉晶体管。 当高电压（即高于接口电路的内部电压）被施加到I / O焊盘时，上拉保护电路将上拉晶体管的栅极驱动到高I / O焊盘电压，以确保没有电流 流向正电源电压。 此外，隔离电路将高I / O焊盘电压耦合到上拉晶体管的主体（阱），以防止由上拉晶体管形成的寄生二极管的漏电流。