公开(公告)号：US06198690B1

公开(公告)日：2001-03-06

申请号：US09503000

申请日：2000-02-14

申请人： Koji Kato ,  Masahiro Kamoshida ,  Shigeo Ohshima

发明人： Koji Kato ,  Masahiro Kamoshida ,  Shigeo Ohshima

IPC分类号： G11C800

CPC分类号： G11C7/225 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/135

摘要： A clock control circuit includes a forward pulse delay circuit including a plurality of delay circuits for delaying a forward pulse signal FCL, a backward pulse delay circuit including a plurality of delay circuits for delaying a backward pulse signal RCL, a state-hold section including a plurality of state-hold circuits for controlling the operation of the backward pulse delay circuit in accordance with the transmission condition of the forward pulse signal in the forward pulse delay circuit, and an input stop circuit for stopping inputting a pulse corresponding to an external clock signal to the backward pulse delay circuit during a predetermined period from the time point when the external clock signal begins to be supplied.

摘要翻译： 时钟控制电路包括：正向脉冲延迟电路，包括用于延迟正向脉冲信号FCL的多个延迟电路;包括用于延迟反向脉冲信号RCL的多个延迟电路的反向脉冲延迟电路;状态保持部分，包括： 多个状态保持电路，用于根据正向脉冲延迟电路中的正向脉冲信号的发送条件控制反向脉冲延迟电路的操作;以及输入停止电路，用于停止输入对应于外部时钟信号的脉冲 在从外部时钟信号开始供给的时刻起的规定期间内向后向脉冲延迟电路发送。

公开(公告)号：US5051954A

公开(公告)日：1991-09-24

申请号：US406420

申请日：1989-09-11

申请人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

发明人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/10

CPC分类号： G11C11/4097 ,  G11C11/408 ,  G11C11/4096

摘要： Memory cells disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by a first gate. One memory cell column in the n memory cell colunns in a selected block is selected by a second gate. One memory cell in a selected memory cell column is selected by a row address. The data in a selected memory cell are stored in a register and output therefrom.

公开(公告)号：US4883978A

公开(公告)日：1989-11-28

申请号：US167082

申请日：1988-03-11

申请人： Shigeo Ohshima ,  Hiroshi Sahara

发明人： Shigeo Ohshima ,  Hiroshi Sahara

IPC分类号： H03K19/00 ,  G11C11/401 ,  G11C11/409 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175

CPC分类号： H03K17/162 ,  H03K19/00361

摘要： For a semiconductor integrated circuit having a data output buffer, separate power source pads and separate reference pads are provided for the data output buffer and the circuit components. Thus, any potential fluctuations or noise generated in the data output buffer are not transmitted to the circuit components, resulting in decreased circuit malfunction.

公开(公告)号：US08000155B2

公开(公告)日：2011-08-16

申请号：US13005582

申请日：2011-01-13

申请人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

发明人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

IPC分类号： G11C7/22 ,  G11C7/06 ,  G11C11/00 ,  G11C17/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/72

摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

公开(公告)号：US07800967B2

公开(公告)日：2010-09-21

申请号：US12324953

申请日：2008-11-28

申请人： Satoru Takase ,  Shigeo Ohshima

发明人： Satoru Takase ,  Shigeo Ohshima

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C7/06 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

摘要： This disclosure concerns a memory including: word lines extending to a first direction; bit lines extending to a second direction crossing the first direction; a memory cell array including cell blocks each including memory cells respectively provided corresponding to intersection points of the word lines and the bit lines; and sense amplifiers provided corresponding to the bit lines, wherein the sense amplifiers copies existing data stored in a first cell block within the memory cell array to a plurality of memory cells, the memory cells being included in second and third cell blocks different from the first cell block, and alternately arranged in an extension direction of the word lines and also alternately arranged in an extension direction of the bit lines, and the sense amplifiers reads data from the second cell block or the third cell block, at a time of outputting data to outside of the sense amplifiers.

摘要翻译： 本公开涉及一种存储器，包括：延伸到第一方向的字线; 位线延伸到与第一方向交叉的第二方向; 包括单元块的存储单元阵列，每个单元块包括分别对应于字线和位线的交点提供的存储单元; 以及对应于所述位线的感测放大器，其中所述感测放大器将存储在所述存储单元阵列内的第一单元块中的现有数据复制到多个存储器单元，所述存储单元包括在与所述第一和第三单元块不同的第二和第三单元块中 并且在字线的延伸方向上交替布置，并且还在位线的延伸方向上交替布置，并且读出放大器在输出数据时从第二单元块或第三单元块读取数据 到感应放大器外面。

公开(公告)号：US07739634B2

公开(公告)日：2010-06-15

申请号：US11742287

申请日：2007-04-30

申请人： Shigeo Ohshima ,  Kiminobu Suzuki

发明人： Shigeo Ohshima ,  Kiminobu Suzuki

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The verification equipment of a semiconductor integrated circuit in the present invention is included with a circuit net list extraction section that extracts the net list of a circuit, a circuit simulation execution section that executes a circuit simulation, based on the extracted net list, a finite impedance judgment section that judges existence or nonexistence of finite impedances, a floating error terminal judgment section that judges existence or nonexistence of floating error terminals by measuring finite impedances, a true floating error terminal judgment section that adds any one of a P channel-type transistor and an N channel-type transistor to terminals of the circuit where it is judged that there are floating error terminals and calculates changes in potential at the terminals and adds the other of the P channel-type transistor and the N channel-type transistor to the terminals and calculates changes in potential at the terminals, and an output section that outputs a judgment result of the floating error terminal judgment section and a judgment result of the true floating error terminal judgment section.

摘要翻译： 本发明的半导体集成电路的验证装置包括：提取电路网列表的电路网列表提取部，基于提取的网表执行电路模拟的电路模拟执行部，有限的 判断有无阻抗的存在或不存在的阻抗判定部，通过测量有限阻抗来判断浮动误差端子的存在或不存在的浮动误差终端判定部;真浮动误差终端判定部，将P沟道型晶体管 和N沟道型晶体管连接到电路的端子，其中判断出存在浮动误差端子并且计算端子处的电位变化，并将另一个P沟道型晶体管和N沟道型晶体管加到 终端，并计算终端的电位变化，以及输出判断输出部 浮动误差终端判断部分的结果和真实浮动错误终端判断部分的判断结果。

公开(公告)号：US20080141196A1

公开(公告)日：2008-06-12

申请号：US11945537

申请日：2007-11-27

申请人： Shigeo Ohshima ,  Kiminobu Suzuki ,  Kazuhiro Yamada ,  Takamichi Arizono

发明人： Shigeo Ohshima ,  Kiminobu Suzuki ,  Kazuhiro Yamada ,  Takamichi Arizono

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A layout-data generation equipment includes a logic circuit designing section which designs a logic circuit based on information of the specifications of a semiconductor integrated circuit, a layout-data generation section which creates layout-data based on the logic circuit, a resistance information extraction section which extracts resistance information of a wire from the layout-data, a circuit simulation execution section which executes a circuit simulation, an identification section of current direction which identifies a direction of a current in the wire based on the resistance information of a wire and an execution result of the circuit simulation, a verification section which verifies whether layout-data of the wire breaks a design rule, the design rule being extracted from the information of the specifications of a semiconductor integrated circuit and the verification section generates this verification result, and a data output section which outputs the layout-data.

摘要翻译： 布局数据生成装置包括逻辑电路设计部，其基于半导体集成电路的规格信息设计逻辑电路，基于逻辑电路生成布局数据的布局数据生成部，电阻信息提取 从布局数据中提取线的电阻信息的部分，执行电路仿真的电路仿真执行部，基于电线的电阻信息识别线中的电流方向的电流方向的识别部，以及 电路仿真的执行结果，验证电线的布局数据是否断开设计规则的验证部分，从半导体集成电路的规格信息中提取设计规则，并且验证部分生成该验证结果， 以及输出布局数据的数据输出部。

公开(公告)号：US06826104B2

公开(公告)日：2004-11-30

申请号：US10227779

申请日：2002-08-26

申请人： Kazuaki Kawaguchi ,  Shigeo Ohshima

发明人： Kazuaki Kawaguchi ,  Shigeo Ohshima

IPC分类号： G11C700

CPC分类号： G11C11/406 ,  G11C11/4076

摘要： In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates “write”, a write operation for a memory cell is performed by a late write scheme. When the second command signal indicates “auto-refresh”, an auto-refresh operation is performed. In the last write cycle of a write operation immediately preceding this auto-refresh operation, addresses for selecting a memory cell as an object of auto-refresh are predetermined. After data write to a memory cell is completed in the last write cycle, row precharge for auto-refresh is performed. After that, an auto-refresh operation (i.e., a data read operation and a data restore operation) is performed for the selected memory cell.

摘要翻译： 在具有迟写功能的FCRAM中，当第一命令信号指示“写活动”时，是否要执行写操作或自动刷新操作是基于第二命令信号确定的。 例如，当第二命令信号指示“写入”时，通过后期写入方案执行存储器单元的写入操作。 当第二命令信号指示“自动刷新”时，执行自动刷新操作。 在紧接在该自动刷新操作之前的写入操作的最后写入周期中，预定用于选择作为自动刷新对象的存储单元的地址。 在最后一个写入周期内对存储单元的数据写入完成后，执行自动刷新的行预充电。 之后，对所选择的存储单元执行自动刷新操作（即，数据读取操作和数据恢复操作）。

公开(公告)号：US06522600B2

公开(公告)日：2003-02-18

申请号：US10163797

申请日：2002-06-04

申请人： Shigeo Ohshima ,  Nobuo Watanabe

发明人： Shigeo Ohshima ,  Nobuo Watanabe

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/409

摘要： A semiconductor memory device comprises first and second pins, a controller, a first command decoder and a lower-side command decoder. The controller is supplied with a signal indicating that a read command is input and a signal indicating that a write command is input based on the signal input to the first pin. The first command decoder is controlled by an output signal of the controller, defines the readout/write operation by use of the first command, fetches an upper-side decode address of a memory cell array via the second pin and decodes the first command. A lower-side command decoder is controlled by an output signal of the controller, fetches a lower-side decode address of the memory cell array via the control pin in response to the second command, decodes the lower-side command, and outputs a lower address latch command, mode register set command and auto-refresh command.

摘要翻译： 半导体存储器件包括第一和第二引脚，控制器，第一命令解码器和下侧命令解码器。 控制器被提供有指示读取命令被输入的信号和表示基于输入到第一引脚的信号来输入写入命令的信号。 第一命令解码器由控制器的输出信号控制，通过使用第一命令定义读/写操作，经由第二引脚取出存储单元阵列的上侧解码地址，并解码第一命令。 下位命令解码器由控制器的输出信号控制，响应于第二命令经由控制引脚取出存储单元阵列的下侧解码地址，对下侧命令进行解码，并输出低位指令译码器 地址锁存命令，模式寄存器设置命令和自动刷新命令。

公开(公告)号：US5311471A

公开(公告)日：1994-05-10

申请号：US987543

申请日：1992-12-07

申请人： Naoki Matsumoto ,  Yuji Wtanabe ,  Shigeo Ohshima

发明人： Naoki Matsumoto ,  Yuji Wtanabe ,  Shigeo Ohshima

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C11/419 ,  G11C7/1048 ,  G11C7/12

摘要： A semiconductor memory device including:a data storage device having a plurality of memory cells each capable of storing a data and being selected by an address, first complementary data corresponding to the data in a selected memory cell being outputted to first complementary data lines;a first equalizer for short-circuiting and equalizing the first complementary data lines;an amplifier for receiving the first complementary data from the first complementary data lines, making large the difference between levels of the first complementary data, and outputting as second complementary data the levels to second complementary data lines;a second equalizer for short-circuiting and equalizing the second complementary data lines;a data latch circuit having latch units and switching means, the latch unit receiving and latching the second complementary data from the second complementary data lines and outputting as third complementary data the second complementary data to third complementary data lines, the switching unit connecting/disconnecting the second complementary data lines, and the switching unit being serially connected to the second complementary data lines between the second equalizer and the latch units; andan output unit for receiving the third complementary data from the third complementary data lines and outputting an output signal corresponding to the third complementary data.

摘要翻译： 一种半导体存储装置，包括：数据存储装置，具有多个存储单元，每个存储单元能够存储数据并由地址选择，对应于所选存储单元中的数据的第一互补数据被输出到第一互补数据线; 用于短路和均衡第一互补数据线的第一均衡器; 放大器，用于从第一互补数据线接收第一互补数据，使得第一互补数据的电平之差变大，并将电平作为第二互补数据输出到第二互补数据线; 第二均衡器，用于短路和均衡第二互补数据线; 具有锁存单元和开关装置的数据锁存电路，所述锁存单元从所述第二互补数据线接收并锁存所述第二互补数据，并将所述第二补充数据作为第三补充数据输出到第三互补数据线，所述切换单元连接/断开 第二互补数据线，并且开关单元串联连接到第二均衡器和锁存单元之间的第二互补数据线; 以及输出单元，用于从第三互补数据线接收第三互补数据，并输出对应于第三互补数据的输出信号。