公开(公告)号：US20220301875A1

公开(公告)日：2022-09-22

申请号：US17837704

申请日：2022-06-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih Wei Lu ,  Chung-Ju Lee ,  Hai-Ching Chen ,  Chien-Hua Huang ,  Tien-I Bao

IPC: H01L21/28 ,  H01L21/768 ,  H01L29/49 ,  H01L23/485

Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

公开(公告)号：US10539751B2

公开(公告)日：2020-01-21

申请号：US16247332

申请日：2019-01-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Hai-Ching Chen ,  Tien-I Bao

IPC: G02B6/42 ,  H01S5/022 ,  H01S5/00

Abstract: A method of making an optical bench includes forming a trench in a substrate and wherein the trench has a sloping side, forming a reflector layer over the sloping side, depositing a redistribution layer over the substrate, disposing an under bump metallization (UBM) layer over the redistribution layer, depositing a passivation layer over the redistribution layer and surrounding sidewalls of the UBM layer, and mounting an optical component over an uppermost portion of the substrate, wherein the optical component is electrically connected to a through substrate via (TSV) extending through the substrate. The reflector layer is configured to reflect an electromagnetic wave from the optical component, and wherein the optical component is mounted outside the trench.

公开(公告)号：US20200003951A1

公开(公告)日：2020-01-02

申请号：US16564456

申请日：2019-09-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hao Tseng ,  Wan-Yu Lee ,  Hai-Ching Chen ,  Tien-I Bao

IPC: G02B6/12 ,  G02B6/138 ,  G02B6/132 ,  G02B6/136

Abstract: A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.

公开(公告)号：US10353147B2

公开(公告)日：2019-07-16

申请号：US15339446

申请日：2016-10-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wan-Yu Lee ,  Ying-Hao Kuo ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/30 ,  H01L21/306 ,  H01L21/308 ,  G02B6/136 ,  C09K13/02 ,  G02B6/42 ,  G02B6/122 ,  G02B6/12

Abstract: A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide.

公开(公告)号：US20180226293A1

公开(公告)日：2018-08-09

申请号：US15942947

申请日：2018-04-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Ching-Yu Chang ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/76837 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2221/1047

Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a metallic material, wherein the first layer includes a trench; and a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

公开(公告)号：US09941157B2

公开(公告)日：2018-04-10

申请号：US14752097

申请日：2015-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Ching-Yu Chang ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/31 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/76837 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2221/1047

Abstract: A method for semiconductor manufacturing includes receiving a device that includes a substrate and a first layer disposed over the substrate, wherein the first layer includes a trench. The method further includes applying a first material over the first layer and filling in the trench, wherein the first material contains a matrix and a porogen that is chemically bonded with the matrix. The method further includes curing the first material to form a porous material layer. The porous material layer has a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed over the first layer. The first and second portions contain substantially the same percentage of each of Si, O, and C. The first and second portions contain substantially the same level of porosity.

公开(公告)号：US20170256486A1

公开(公告)日：2017-09-07

申请号：US15601562

申请日：2017-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Hsu Wu ,  Hai-Ching Chen ,  Jung-Hsun Tsai ,  Shau-Lin Shue ,  Tien-I Bao

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/532

Abstract: A first conductive element is disposed. in a first dielectric layer. An etching stop layer is disposed on the first dielectric layer but not on the first conductive element. A first metal capping layer segment is disposed on the first conductive element but not on the first dielectric layer. The etching stop layer has a greater thickness than the first metal capping layer segment. A first segment of a second conductive element is disposed on the first metal capping layer segment. A second segment of the second conductive element is disposed over the first segment of the second conductive element and partially over the etching stop layer. A third conductive element is disposed over the second conductive element.

公开(公告)号：US20170075065A1

公开(公告)日：2017-03-16

申请号：US15342669

申请日：2016-11-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kai-Fang Cheng ,  Hai-Ching Chen ,  Tien-I Bao

IPC: G02B6/132 ,  H01L21/56 ,  H01L21/48 ,  G02B6/136 ,  G02B6/122

CPC classification number: G02B6/132 ,  G02B6/122 ,  G02B6/136 ,  G02B6/138 ,  G02B2006/12104 ,  H01L21/48 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3192 ,  H01L29/06 ,  H01L2224/73204

Abstract: A method comprises forming a plateau region and a trench region over a substrate, wherein the trench region comprises a slope and a flat bottom, depositing a reflecting layer over the flat bottom and a portion of the slope, depositing a first adhesion promoter layer over the reflecting layer, applying a first curing process to the first adhesion promoter layer, wherein, after the first curing process finishes, the reflecting layer and the first adhesion promoter layer form a first bonding interface, depositing a bottom cladding layer deposited over the first adhesion promoter layer, applying a second curing process to the bottom cladding layer to form a second bonding interface layer, depositing a core layer over the bottom cladding layer and depositing a top cladding layer over the core layer.

Abstract translation: 一种方法包括在衬底上形成平坦区域和沟槽区域，其中沟槽区域包括斜面和平坦的底部，在平坦底部和斜面的一部分上沉积反射层，在第一粘附促进层上方沉积 反应层，对第一粘合促进剂层施加第一固化过程，其中，在第一固化过程结束后，反射层和第一粘合促进剂层形成第一粘合界面，沉积沉积在第一粘合促进剂上的底部包层 将第二固化过程施加到底部包层以形成第二接合界面层，将芯层沉积在底部包层上并在芯层上沉积顶部覆层。

公开(公告)号：US20170053809A1

公开(公告)日：2017-02-23

申请号：US15345780

申请日：2016-11-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wan-Yu Lee ,  Ying-Hao Kuo ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/306 ,  C09K13/04 ,  G01N21/33 ,  H01L21/66 ,  H01L21/67

CPC classification number: H01L21/30604 ,  C09K13/04 ,  G01N21/33 ,  H01L21/0206 ,  H01L21/306 ,  H01L21/30608 ,  H01L21/31133 ,  H01L21/67075 ,  H01L21/67086 ,  H01L21/67253 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration. Then, based upon such measurement, a makeup amount of the components may be added be a makeup unit to the etching solution to control the concentration of the components within the etching system.

Abstract translation: 提供了蚀刻半导体器件的系统和方法。 蚀刻溶液由监测单元取样和分析，以确定蚀刻溶液中组分的浓度，例如氧化剂浓度。 然后，基于这样的测量，可以将组分的补充量添加到蚀刻溶液中的化妆单元以控制蚀刻系统内的组分的浓度。

公开(公告)号：US20170033043A1

公开(公告)日：2017-02-02

申请号：US14813177

申请日：2015-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Bo-Jiun Lin ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/522 ,  H01L21/02 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L21/02203 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L29/0649 ,  H01L2221/1047

Abstract: The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

Abstract translation: 本发明涉及形成多孔低k电介质结构。 在衬底上形成多个导电元件。 导电元件通过多个开口彼此分离。 在导电元件上形成阻挡层。 阻挡层形成为覆盖开口的侧壁。 对阻挡层进行处理。 在执行处理过程之后，阻挡层变为亲水性。 在执行处理处理之后，在阻挡层上形成电介质材料。 电介质材料填充开口并含有多个致孔剂。