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公开(公告)号：US11372715B2
公开(公告)日：2022-06-28
申请号：US16790444
申请日：2020-02-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Saket Jalan , Indu Prathapan , Abhishek Ganapati Karkisaval
Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.
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公开(公告)号：US10768278B2
公开(公告)日：2020-09-08
申请号：US15333593
申请日：2016-10-25
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Indu Prathapan , Karthik Ramasubramanian , Brian P. Ginsburg
Abstract: A FMCW radar system with a built-in self-test (BIST) system for monitoring includes a receiver, a transmitter, and a frequency synthesizer. A FMCW chirp timing engine controls timing of operations at least one radar component. The BIST system includes at least one switchable coupling for coupling a first plurality of different analog signals including from a first plurality of selected nodes in the receiver or transmitter that are all coupled to a second number of monitor analog-to-digital converters (ADCs). The second number is less than (
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公开(公告)号：US20200210072A1
公开(公告)日：2020-07-02
申请号：US16235897
申请日：2018-12-28
Applicant: Texas Instruments Incorporated
Inventor： Puneet Sabbarwal , Indu Prathapan
Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.
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公开(公告)号：US10372531B2
公开(公告)日：2019-08-06
申请号：US15653749
申请日：2017-07-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Indu Prathapan , Prashanth Saraf , Desmond Pravin Martin Fernandes , Saket Jalan
Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.
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公开(公告)号：US09680677B2
公开(公告)日：2017-06-13
申请号：US14528660
申请日：2014-10-30
Applicant: Texas Instruments Incorporated
Inventor： Sriram Murali , Indu Prathapan , Pankaj Gupta , Zahir Ibrahim Parkar , Sundarrajan Rangachari
IPC: H04L27/14 , H04L27/156 , H04L27/34 , H04W52/02
CPC classification number: H04L27/1566 , H04L27/3455 , H04W52/0229 , Y02D70/00
Abstract: A weather band receiver, which may be part of an FM receiver, is disclosed. FSK-encoded data units in an alert packet transmission are detected using a quadrature matched filter circuit. At least one FSK-encoded data unit is captured from the alert packet transmission. Soft quantized bits are extracted from the FSK-encoded data units. The soft quantized bits are saved to memory and used to recover an alert message. Soft quantized bits from two or more FSK-encoded data units may be combined before recovering the alert message.
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Patent Agency Ranking
公开(公告)号：US11789137B2
公开(公告)日：2023-10-17
申请号：US17138549
申请日：2020-12-30
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Sreekiran Samala , Indu Prathapan
CPC classification number: G01S13/345 , G01S7/032 , G01S7/352 , H03C3/0925 , H03L7/087 , H03L7/099
Abstract: In described examples, a frequency modulated continuous wave (FMCW) synthesizer includes a control engine, and a phase locked loop (PLL) including a frequency divider, a control voltage generator (CVG), and a voltage controlled oscillator (VCO). The frequency divider modifies a VCO output frequency based on a control input. The CVG generates a control voltage based on a frequency reference and the frequency divider output. The VCO outputs a FMCW output having the VCO output frequency in response to the control voltage. The control engine generates the control input so that the VCO output frequency: from a first time to a second time, is a first frequency; from the second time to a third time, changes at a first rate; from the third time to a fourth time, changes at a second rate different from the first rate; and from the fourth time to a fifth time, is a second frequency.
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公开(公告)号：US11579242B2
公开(公告)日：2023-02-14
申请号：US16442152
申请日：2019-06-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sandeep Rao , Karthik Ramasubramanian , Indu Prathapan , Raghu Ganesan , Pankaj Gupta
Abstract: A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.
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公开(公告)号：US11537309B2
公开(公告)日：2022-12-27
申请号：US16995542
申请日：2020-08-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Puneet Sabbarwal , Indu Prathapan
Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.
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公开(公告)号：US20220283899A1
公开(公告)日：2022-09-08
申请号：US17824605
申请日：2022-05-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Saket Jalan , Indu Prathapan , Abhishek Ganapati Karkisaval
Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.
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公开(公告)号：US11170071B2
公开(公告)日：2021-11-09
申请号：US16221470
申请日：2018-12-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Indu Prathapan , Sai Ram Prakash Jayanthi
Abstract: A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.
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