公开(公告)号：US20150349092A1

公开(公告)日：2015-12-03

申请号：US14821085

申请日：2015-08-07

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/417 ,  H01L21/324 ,  H01L21/225 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/66712 ,  H01L21/225 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7813

Abstract: A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.

公开(公告)号：US20150221747A1

公开(公告)日：2015-08-06

申请号：US14688639

申请日：2015-04-16

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L29/66 ,  H01L29/201 ,  H01L21/8232 ,  H01L49/02 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/8232 ,  H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7833

Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

Abstract translation: 半导体器件包括具有电耦合到GaN FET的漏极节点并且与降压部件串联耦合的过压钳位部件的GaN FET。 降压组件电耦合到为GaN FET提供截止状态偏置的端子。 当GaN FET的漏极节点处的电压小于GaN FET的击穿电压时，过电压钳位部件导通无效电流，并且当电压上升到高于安全电压限度时，导通显着的电流。 降压部件被配置为提供随着来自过电压钳位部件的电流增加而增加的电压降。 半导体器件被配置为当跨越降压元件的电压降达到阈值时接通GaN FET。

公开(公告)号：US20150179793A1

公开(公告)日：2015-06-25

申请号：US14559239

申请日：2014-12-03

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Philip L. HOWER ,  Sameer PENDHARKAR

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/225 ,  H01L29/10 ,  H01L21/324 ,  H01L21/266 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L21/225 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7823 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

Abstract translation: 一种集成电路，其包含延伸漏极MOS晶体管，其具有漂移层，在上部RESURF层上并接触漂移层的上表面，以及在漂移层下面的埋入漏极延伸层，该漏极延伸层与漏极的漂移层电连接 在通道端处与漂移层分离。 可以在通道端处的漂移层和埋漏极延伸部之间形成较低的RESURF层。 上部RESURF层，漂移层，下部RESURF层和掩埋漏极延伸中的任何一个可以具有从漏极端到沟道端的渐变掺杂密度。 形成包含具有漂移层的延伸漏极MOS晶体管的集成电路的工艺，上部RESURF层和掩埋漏极延伸。

公开(公告)号：US20130157429A1

公开(公告)日：2013-06-20

申请号：US13765054

申请日：2013-02-12

Applicant: Texas Instruments Incorporated

Inventor： Pinghai HAO ,  Sameer PENDHARKAR ,  Binghua HU ,  Qingfeng WANG

IPC: H01L21/8234

CPC classification number: H01L29/0847 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.

Abstract translation: 包含扩展漏极MOS晶体管的集成电路可以通过形成具有掩模手指的沟道区域的漂移区域注入掩模来形成，并且延伸到源极/沟道有源区，但不延伸到漏极接触有源区。 通过暴露的指状物注入的掺杂剂在掩模指下面的衬底中形成横向掺杂条纹。 栅极下方的漂移区域的平均掺杂密度比漏极接触有效面积处的漂移区域的平均掺杂密度小至少25％。 在一个实施例中，掺杂剂横向漫射以形成连续漂移区域。 在另一个实施例中，横向掺杂条纹之间的衬底材料与横向掺杂条纹保持相反的导电类型。

公开(公告)号：US20200303535A1

公开(公告)日：2020-09-24

申请号：US16895111

申请日：2020-06-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jungwoo JOH ,  Naveen TIPIRNENI ,  Chang Soo SUH ,  Sameer PENDHARKAR

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L29/06 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US20180188313A1

公开(公告)日：2018-07-05

申请号：US15395907

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alex PAIKIN ,  Colin JOHNSON ,  Tathagata CHATTERJEE ,  Sameer PENDHARKAR

IPC: G01R31/26 ,  G01R31/28

CPC classification number: G01R31/2628 ,  G01R31/2849

Abstract: In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.

公开(公告)号：US20170098702A1

公开(公告)日：2017-04-06

申请号：US15380280

申请日：2016-12-15

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L29/778 ,  H01L49/02 ,  H01L27/02 ,  H01L29/205 ,  H01L29/20 ,  H01L27/06

CPC classification number: H01L29/7787 ,  H01L21/8232 ,  H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7833

Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

公开(公告)号：US20160043236A1

公开(公告)日：2016-02-11

申请号：US14923125

申请日：2015-10-26

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland HOWER ,  Sameer PENDHARKAR ,  Marie DENISON

IPC: H01L29/808 ,  H01L21/32 ,  H01L21/266 ,  H01L27/098 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8232 ,  H01L29/66 ,  H01L21/225

CPC classification number: H01L29/808 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/32 ,  H01L21/8232 ,  H01L27/098 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/36 ,  H01L29/66901

Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.

公开(公告)号：US20150287641A1

公开(公告)日：2015-10-08

申请号：US14745749

申请日：2015-06-22

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L21/8236 ,  H01L29/16 ,  H01L29/20 ,  H01L21/8234

CPC classification number: H03K17/6872 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/7833 ,  H02M5/2573 ,  H03F3/193 ,  H03F3/195 ,  H03K17/6871 ,  H03K17/6877 ,  H03K2017/6875

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

Abstract translation: 半导体器件包括耗尽型GaN FET和集成驱动器/共源共栅IC。 集成驱动器/共源共极集成电路包括与GaN FET的源极节点串联连接的增强型共模NMOS晶体管。 集成驱动器/共源共极IC还包括驱动电路，其调节栅极输入信号并向级联的NMOS晶体管的栅极节点提供合适的数字波形。 级联的NMOS晶体管和驱动电路形成在相同的硅衬底上。

公开(公告)号：US20150243742A1

公开(公告)日：2015-08-27

申请号：US14706595

申请日：2015-05-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/404 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66871 ,  H01L29/78 ,  H01L29/812

Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.

Abstract translation: 半导体器件在至少三个连续区域上形成有台阶式场板，其中在阶梯式场板下的总电介质厚度与先前区域相比在每个区域中至少为10％以上。 各区域的总电介质厚度均匀。 阶梯式场板形成在至少两个电介质层上，至少两个电介质层至少形成一个电介质层，使得图案化的电介质层的至少一部分在阶梯式场板的一个或多个区域中被去除。