公开(公告)号：US20200183787A1

公开(公告)日：2020-06-11

申请号：US16789672

申请日：2020-02-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Siva Srinivas Kothamasu

IPC: G06F11/10 ,  G11C29/52 ,  G06F13/16

Abstract: In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

公开(公告)号：US10572344B2

公开(公告)日：2020-02-25

申请号：US15961010

申请日：2018-04-24

Applicant: Texas Instruments Incorporated

Inventor： Siva Srinivas Kothamasu

IPC: G06F11/10 ,  G06F13/16 ,  G11C29/52 ,  G11C29/04 ,  G11C5/04

Abstract: In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

公开(公告)号：US10387690B2

公开(公告)日：2019-08-20

申请号：US15493973

申请日：2017-04-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Siva Srinivas Kothamasu ,  Haydar Bilhan

IPC: G06K7/00 ,  G06F1/26 ,  G11C5/14

Abstract: This invention is an SOC with an integrated single rail power supply that interfaces with the host controller and dynamically changes the host interface supply to 3.3 volts or 1.8 volts based on the sensed card speed grade. The SOC initially selects 3.3 volts to supply to the memory card. The SOC communicates with memory card vis input/output circuits to determine a memory type. The controller selects a 3.3 volt or 1.8 volt supply for the memory card based upon the determination. The SOC powers the input/output circuits at the same supply voltage as the memory card. This invention employs 1.8 volt transistors in the input/output circuits using a bias voltage to protect these transistor from the full 3.3 volt power when the memory card is powered to 3.3 volts.

公开(公告)号：US12141030B2

公开(公告)日：2024-11-12

申请号：US18361995

申请日：2023-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Siva Srinivas Kothamasu

IPC: G06F11/10 ,  G06F13/16 ,  G11C5/04 ,  G11C29/04 ,  G11C29/52

Abstract: In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

公开(公告)号：US20230376377A1

公开(公告)日：2023-11-23

申请号：US18361995

申请日：2023-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Siva Srinivas Kothamasu

IPC: G06F11/10 ,  G11C29/52 ,  G06F13/16 ,  G11C29/04 ,  G11C5/04

CPC classification number: G06F11/1068 ,  G11C29/52 ,  G06F11/1048 ,  G06F13/1668 ,  G11C2029/0411 ,  G11C5/04 ,  G06F2213/0016

Abstract: In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

公开(公告)号：US11714713B2

公开(公告)日：2023-08-01

申请号：US17878149

申请日：2022-08-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Siva Srinivas Kothamasu

IPC: G06F11/10 ,  G06F13/16 ,  G11C29/52 ,  G11C29/04 ,  G11C5/04

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F13/1668 ,  G11C29/52 ,  G06F2213/0016 ,  G11C5/04 ,  G11C2029/0411

Abstract: In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

公开(公告)号：US20230205305A1

公开(公告)日：2023-06-29

申请号：US18060114

申请日：2022-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Kowkutla ,  Chunhua Hu ,  Raghavendra Santhanagopal ,  Kazunobu Shin ,  Charles Gerlach ,  Rejitha Nair ,  Ritesh Sojitra ,  Sai Rajaraman ,  Anthony Seely ,  Siva Srinivas Kothamasu ,  Varun Singh ,  John Apostol

IPC: G06F1/3287 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F1/3287 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/423

Abstract: A circuit device is provided and includes a first power domain comprising a universal serial bus (USB) subsystem and/or a memory controller subsystem. The first power domain is configured to isolate the USB subsystem and/or the memory controller subsystem from a power-on-reset signal asserted during a low power mode.

公开(公告)号：US20160351247A1

公开(公告)日：2016-12-01

申请号：US15236797

申请日：2016-08-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prajkta Vyavahare ,  Rajat Chauhan ,  Siva Srinivas Kothamasu

IPC: G11C11/4093 ,  G11C11/4074 ,  G06F13/10 ,  G11C11/4094

CPC classification number: G11C11/4093 ,  G06F1/3296 ,  G06F13/102 ,  G11C7/1057 ,  G11C11/4074 ,  G11C11/4094 ,  H03K17/687 ,  Y02D10/14

Abstract: The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold.

Abstract translation: 本公开提供了由输入/输出（IO）电源电压供电的输入/输出（IO）电路。 IO电路包括接收第一反相信号，IO电源电压，偏置电压和焊盘电压的截止电路。 输出级与断路电路相连。 输出级接收第一信号，第二信号和偏置电压。 焊盘耦合到输出级，并且在焊盘处产生的电压是焊盘电压。 当IO电源电压转换低于定义的阈值时，截止电路和输出级将焊盘电压保持在逻辑高电平。

公开(公告)号：US09471140B2

公开(公告)日：2016-10-18

申请号：US14304795

申请日：2014-06-13

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland GmbH

Inventor： Kazunobu Shin ,  Siva Srinivas Kothamasu ,  James John Doublesin ,  Roland Volker Bucksch

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/324 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: A system having multiple power mode types, for example, includes a power manager that is responsive to a selection of a suspend power mode type for maintaining processor context information in volatile memory while the processor is in the selected suspend mode. A status register is arranged to retain the status of the context information in the volatile memory while the processor is in the selected suspend power mode. The power manager is arranged to selectively apply power to various voltage domains in response to the type of power mode selected. The processor is optionally arranged to signal the power manager of transitions to the selected suspend mode and of transitions to an active mode using a power enable signal.

Abstract translation: 例如，具有多个功率模式类型的系统包括功率管理器，该功率管理器响应于在处理器处于所选择的挂起模式时在易失性存储器中维持处理器上下文信息的暂停功率模式类型的选择。 状态寄存器被布置成在处理器处于选择的挂起电源模式时将上下文信息的状态保持在易失性存储器中。 功率管理器被布置为响应于所选择的功率模式的类型选择性地向各个电压域施加功率。 处理器可选地布置成使用功率使能信号向功率管理器发信号通知转换到所选择的暂停模式和转换到活动模式。