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    Faster and more efficient different precision sum of absolute differences for dynamically configurable block searches for motion estimation
    12.
    发明授权
    Faster and more efficient different precision sum of absolute differences for dynamically configurable block searches for motion estimation 有权
    更快，更高效的不同精度的绝对差异和动态可配置块搜索的运动估计

    公开(公告)号：US09582273B2

    公开(公告)日：2017-02-28

    申请号：US14327002

    申请日：2014-07-09

    Applicant: Texas Instruments Incorporated

    Inventor： Mujibur Rahman ,  Djordje Senicic ,  Timothy D. Anderson

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: H04N19/56 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3853 ,  G06F9/3893 ,  G06F2207/5442 ,  H04N19/433 ,  H04N19/521

    Abstract: This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.

    Abstract translation: 本发明是在单个操作中形成多个绝对值（SAD）的数字信号处理器。 执行包括两组多行的绝对值操作之和的操作单元，每行产生SAD输出。 多个绝对值差分单元接收相应的压缩候选像素数据和压缩参考像素数据。 行夏天对行中的绝对值差单位的输出求和。 候选像素相对于参考像素相对于一组行中的每个后续行偏移一个像素。 两组行在包含在指令指定操作数中的候选像素的相对的两半上进行操作。 可以使用绝对差分单位和行夏季的进位链控制在不同的数据宽度上执行SAD操作。

    Secure Master and Secure Guest Endpoint Security Firewall
    15.
    发明申请
    Secure Master and Secure Guest Endpoint Security Firewall 审中-公开
    安全主控和安全访客端点安全防火墙

    公开(公告)号：US20140143849A1

    公开(公告)日：2014-05-22

    申请号：US14062002

    申请日：2013-10-24

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy D. Anderson ,  Joseph R. M. Zbiciak ,  Matthew D. Pierson ,  Kai Chirca

    IPC: H04L29/06

    CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    Abstract: This invention is a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.

    Abstract translation: 本发明是具有安全层级的安全防火墙，包括：安全主机（SM）; 安全客人（SG）; 和非安全（NS）。 有一个安全的主人和n个安全的客人。 防火墙包括一个用于安全主控的安全区域和一个用于安全访客的安全区域。 SM区域仅允许从安全主机访问，并且SG区域允许来自任何安全事务的访问。 最后，非安全区域可以实现两种方式。 在第一个选项中，只有在非安全事务时才可以访问非安全区域。 在第二个选项中，非安全区域可以被访问任何处理核心。 在第二个选项中，如果安全身份是安全主机或安全访客，则访问权限降级到非安全访问。 如果不需要两个安全级别，则安全主机可以解锁SM区域，以允许任何安全访客访问SM区域。

    Multi Processor Multi Domain Conversion Bridge with Out of Order Return Buffering
    16.
    发明申请
    Multi Processor Multi Domain Conversion Bridge with Out of Order Return Buffering 有权
    多处理器多域转换桥与乱序返回缓冲

    公开(公告)号：US20140115210A1

    公开(公告)日：2014-04-24

    申请号：US14056729

    申请日：2013-10-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai Chirca ,  Daniel B. Wu ,  Matthew D. Pierson ,  Timothy D. Anderson

    IPC: G06F13/16

    CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

    Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the bus protocols used by each individual processor within the attached subsystem, and can perform the appropriate protocol conversion on each processor's transactions to adapt the transaction to/from the bus protocol used by the interconnect.

    Abstract translation: 在高速缓存一致主机和相干系统互连之间实现异步双域网桥。 该桥具有两个半部分，每个时钟/电源下降域主和互连中一个。 异步网桥了解连接子系统内每个处理器所使用的总线协议，并且可以对每个处理器的事务执行适当的协议转换，以使交易与互连使用的总线协议相适应。

    STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING
    17.
    发明申请
    STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING 有权

    公开(公告)号：US20250013518A1

    公开(公告)日：2025-01-09

    申请号：US18892677

    申请日：2024-09-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph Zbiciak ,  Timothy D. Anderson ,  Duc Bui ,  Kai Chirca

    IPC: G06F11/07 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F11/27 ,  G06F11/30 ,  G06F11/36 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/16

    Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

    Streaming engine with deferred exception reporting
    19.
    发明授权
    Streaming engine with deferred exception reporting 有权

    公开(公告)号：US11573847B2

    公开(公告)日：2023-02-07

    申请号：US16988500

    申请日：2020-08-07

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph Zbiciak ,  Timothy D. Anderson ,  Duc Bui ,  Kai Chirca

    IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30 ,  G06F12/0875 ,  G06F12/0862 ,  G06F11/27 ,  G06F13/16 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/36 ,  G06F11/10

    Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

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