公开(公告)号：US20210013229A1

公开(公告)日：2021-01-14

申请号：US17028748

申请日：2020-09-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Haruka SAKUMA ,  Hidenori MIYAGAWA ,  Shosuke FUJI ,  Kiwamu SAKUMA ,  Fumitaka ARAI ,  Kunifumi SUZUKI

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/51 ,  H01L21/28

Abstract: A semiconductor memory device comprises: a substrate; a first semiconductor portion provided separated from the substrate in a first direction intersecting a surface of the substrate, the first semiconductor portion extending in a second direction intersecting the first direction; a first gate electrode extending in the first direction; a first insulating portion which is provided between the first semiconductor portion and the first gate electrode, includes hafnium (Hf) and oxygen (O), and includes an orthorhombic crystal as a crystal structure; a first conductive portion provided between the first semiconductor portion and the first insulating portion; and a second insulating portion provided between the first semiconductor portion and the first conductive portion. An area of a facing surface of the first conductive portion facing the first semiconductor portion is larger than an area of a facing surface of the first conductive portion facing the first gate electrode.

公开(公告)号：US20200303403A1

公开(公告)日：2020-09-24

申请号：US16559389

申请日：2019-09-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keisuke NAKATSUKA ,  Fumitaka ARAI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor memory device includes a first block and a second block arranged adjacent to each other in a Y direction. Each of the first and second blocks includes conductive layers extended in an X direction, memory trenches between the conductive layers, memory pillars provided across two conductive layers with a memory trench interposed therebetween, and transistors provided between the memory pillars and the conductive layers. One of the conductive layers provided at an end of the first block in the Y direction is electrically connected to one of the conductive layers provided at an end of the second block.

公开(公告)号：US20200286828A1

公开(公告)日：2020-09-10

申请号：US16564584

申请日：2019-09-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiji HOSOTANI ,  Fumitaka ARAI ,  Keisuke NAKATSUKA ,  Nobuyuki MOMO ,  Motohiko FUJIMATSU

IPC: H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L23/522

Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer including first to third portions which are arranged along a first direction and differ in position from one another in a second direction; a conductive layer including a fourth portion extending in the second direction and a fifth portion extending in the first direction; a first insulating layer between the fourth portion and the first semiconductor layer and between the fifth portion and the first semiconductor layer; a first contact plug coupled to the fourth portion; a second contact plug coupled to the first semiconductor layer in a region where the first insulating layer is formed; a first interconnect; and a first memory cell apart from the fifth portion in the first direction and storing information between the semiconductor layer and the first interconnect.

公开(公告)号：US20200098784A1

公开(公告)日：2020-03-26

申请号：US16297079

申请日：2019-03-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi NAGASHIMA ,  Fumitaka ARAI

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/528 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768

Abstract: According to one embodiment, a semiconductor memory includes: a first member extending in a first direction perpendicular to a surface of a substrate, and including a first semiconductor layer; first and second interconnects extending in a second direction parallel to the surface of the substrate, the second interconnect neighboring the first interconnect in a third direction; a second member extending in the first direction and above the first member, the second member including a second semiconductor layer; third and a fourth interconnects extending in the second direction, the fourth interconnect neighboring the third interconnect in the third direction; and a third semiconductor layer between the first and the second members, the third semiconductor layer being continuous with the first and the second semiconductor layers.

公开(公告)号：US20190181150A1

公开(公告)日：2019-06-13

申请号：US15929102

申请日：2019-02-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Wataru SAKAMOTO ,  Ryota SUZUKI ,  Tatsuya OKAMOTO ,  Tatsuya KATO ,  Fumitaka ARAI

IPC: H01L27/11556 ,  H01L29/792 ,  H01L29/66 ,  H01L29/06 ,  G11C16/04 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11519

Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.

公开(公告)号：US20190074066A1

公开(公告)日：2019-03-07

申请号：US15923501

申请日：2018-03-16

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yusuke SHIMADA ,  Fumitaka ARAI ,  Tatsuya KATO

IPC: G11C16/26 ,  G11C16/04 ,  H01L27/1157

Abstract: A semiconductor memory device includes a first NAND string and a second NAND string sharing a channel and being connected in parallel. When reading a value from a first memory cell transistor of the first NAND string, a first potential is applied to a gate of a second memory cell transistor of the first NAND string and a gate of at least one of fourth memory cell transistors opposing the second memory cell transistor, a second potential is applied to a gate of a third memory cell transistor of the second NAND string opposing the first memory cell transistor, and a gate potential of the first memory cell transistor is swept between the second potential and the first potential. The second potential is lower than the first potential.

公开(公告)号：US20180261623A1

公开(公告)日：2018-09-13

申请号：US15688561

申请日：2017-08-28

Applicant: Toshiba Memory Corporation

Inventor： Kazuyuki HIGASHI ,  Kazumichi TSUMURA ,  Ryota KATSUMATA ,  Fumitaka ARAI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11568 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.

公开(公告)号：US20170352672A1

公开(公告)日：2017-12-07

申请号：US15686292

申请日：2017-08-25

Applicant: Toshiba Memory Corporation

Inventor： Wataru SAKAMOTO ,  Tatsuya KATO ,  Yuta WATANABE ,  Katsuyuki SEKINE ,  Toshiyuki IWAMOTO ,  Fumitaka ARAI

IPC: H01L27/11556 ,  H01L23/528

CPC classification number: H01L27/11556 ,  H01L23/528 ,  H01L27/11521

Abstract: A semiconductor memory device according to an embodiment includes first and second semiconductor pillars extending in a first direction and being arranged along a second direction, first and second interconnects extending in a third direction and being provided between the first semiconductor pillar and the second semiconductor pillar, a first electrode provided between the first semiconductor pillar and the first interconnect, a second electrode provided between the second semiconductor pillar and the second interconnect, third and fourth interconnects extending in the second direction, a first contact contacting the first semiconductor pillar and being connected to the third interconnect, and a second contact contacting the second semiconductor pillar and being connected to the fourth interconnect. The third and fourth interconnects each pass through both a region directly above the first semiconductor pillar and a region directly above the second semiconductor pillar.