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    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190181150A1

    公开(公告)日：2019-06-13

    申请号：US15929102

    申请日：2019-02-05

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Wataru SAKAMOTO ,  Ryota SUZUKI ,  Tatsuya OKAMOTO ,  Tatsuya KATO ,  Fumitaka ARAI

    IPC: H01L27/11556 ,  H01L29/792 ,  H01L29/66 ,  H01L29/06 ,  G11C16/04 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11519

    Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME 审中-公开

    公开(公告)号：US20190074066A1

    公开(公告)日：2019-03-07

    申请号：US15923501

    申请日：2018-03-16

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Yusuke SHIMADA ,  Fumitaka ARAI ,  Tatsuya KATO

    IPC: G11C16/26 ,  G11C16/04 ,  H01L27/1157

    Abstract: A semiconductor memory device includes a first NAND string and a second NAND string sharing a channel and being connected in parallel. When reading a value from a first memory cell transistor of the first NAND string, a first potential is applied to a gate of a second memory cell transistor of the first NAND string and a gate of at least one of fourth memory cell transistors opposing the second memory cell transistor, a second potential is applied to a gate of a third memory cell transistor of the second NAND string opposing the first memory cell transistor, and a gate potential of the first memory cell transistor is swept between the second potential and the first potential. The second potential is lower than the first potential.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20170352672A1

    公开(公告)日：2017-12-07

    申请号：US15686292

    申请日：2017-08-25

    Applicant: Toshiba Memory Corporation

    Inventor： Wataru SAKAMOTO ,  Tatsuya KATO ,  Yuta WATANABE ,  Katsuyuki SEKINE ,  Toshiyuki IWAMOTO ,  Fumitaka ARAI

    IPC: H01L27/11556 ,  H01L23/528

    CPC classification number: H01L27/11556 ,  H01L23/528 ,  H01L27/11521

    Abstract: A semiconductor memory device according to an embodiment includes first and second semiconductor pillars extending in a first direction and being arranged along a second direction, first and second interconnects extending in a third direction and being provided between the first semiconductor pillar and the second semiconductor pillar, a first electrode provided between the first semiconductor pillar and the first interconnect, a second electrode provided between the second semiconductor pillar and the second interconnect, third and fourth interconnects extending in the second direction, a first contact contacting the first semiconductor pillar and being connected to the third interconnect, and a second contact contacting the second semiconductor pillar and being connected to the fourth interconnect. The third and fourth interconnects each pass through both a region directly above the first semiconductor pillar and a region directly above the second semiconductor pillar.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210288057A1

    公开(公告)日：2021-09-16

    申请号：US17331147

    申请日：2021-05-26

    Applicant: Toshiba Memory Corporation

    Inventor： Satoshi NAGASHIMA ,  Tatsuya KATO ,  Wataru SAKAMOTO

    IPC: H01L27/11556 ,  G11C16/04 ,  G11C16/10 ,  H01L29/788 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11521

    Abstract: A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.

    SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF 审中-公开

    公开(公告)号：US20200090752A1

    公开(公告)日：2020-03-19

    申请号：US16296100

    申请日：2019-03-07

    Applicant: Toshiba Memory Corporation

    Inventor： Tatsuya KATO ,  Yusuke SHIMADA ,  Fumitaka ARAI

    IPC: G11C16/04 ,  G11C16/26 ,  H01L27/11582 ,  H01L27/1157

    Abstract: A semiconductor memory device of an embodiment includes a substrate, a first conductive layer provided above the substrate, the first conductive layer being spaced apart from the substrate in a first direction, and the first conductive layer being provided parallel to a substrate plane, a second conductive layer provided adjacent to the first conductive layer in a second direction intersecting the first direction, the second conductive layer being provided parallel to the substrate plane, a third conductive layer provided above the first conductive layer, the third conductive layer being spaced apart from the first conductive layer in the first direction, and the third conductive layer being provided parallel to the substrate plane, a fourth conductive layer provided above the second conductive layer, the fourth conductive layer being spaced apart from the second conductive layer in the first direction, and the fourth conductive layer being provided parallel to the substrate plane, a fifth conductive layer provided above the third conductive layer, the fifth conductive layer being spaced apart from the third conductive layer in the first direction, and the fifth conductive layer being provided parallel to the substrate plane, a sixth conductive layer provided above the fourth conductive layer, the sixth conductive layer being spaced apart from the fourth conductive layer in the first direction, and the sixth conductive layer being provided parallel to the substrate plane, an insulator provided between the first and second conductive layers, between the third and fourth conductive layers, and between the fifth and sixth conductive layers, a first signal line provided between the first, third, and fifth conductive layers and the insulator, the first signal line extending in the first direction, a second signal line provided between the second, fourth, and sixth conductive layers and the insulator, the second signal line extending in the first direction, a first memory cell provided between the first conductive layer and the first signal line, the first memory cell being configured to store first information, a second memory cell provided between the second conductive layer and the second signal line, the second memory cell being configured to store second information, a third memory cell provided between the third conductive layer and the first signal line, the third memory cell being configured to store third information, a fourth memory cell provided between the fourth conductive layer and the second signal line, the fourth memory cell being configured to store fourth information, a fifth memory cell provided between the fifth conductive layer and the first signal line, the fifth memory cell being configured to store fifth information, a sixth memory cell provided between the sixth conductive layer and the second signal line, the sixth memory cell being configured to store sixth information, and a control circuit configured to apply a second voltage to the third conductive layer, the control circuit being configured to apply a third voltage to the fifth conductive layer, the control circuit being configured to read data from the first memory cell, the second voltage being smaller than a first voltage, the first voltage being applied to the first conductive layer, and the third voltage being larger than the first voltage.

    STACKED TYPE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    9.
    发明申请
    STACKED TYPE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20180083022A1

    公开(公告)日：2018-03-22

    申请号：US15822860

    申请日：2017-11-27

    Applicant: Toshiba Memory Corporation

    Inventor： Tatsuya KATO ,  Wataru SAKAMOTO ,  Fumitaka ARAI

    IPC: H01L27/11556 ,  H01L27/11548 ,  H01L27/11519

    CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11548

    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.

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