公开(公告)号：US20210043546A1

公开(公告)日：2021-02-11

申请号：US17079736

申请日：2020-10-26

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito YOSHIMIZU ,  Yoshiro SHIMOJO ,  Shinya ARAI

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/522

Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

公开(公告)号：US20200185221A1

公开(公告)日：2020-06-11

申请号：US16559518

申请日：2019-09-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yasuhito YOSHIMIZU ,  Fuyuma ITO ,  Hakuba KITAGAWA ,  Yohei YAMAMOTO ,  Hisashi OKUCHI ,  Yuji YAMADA

IPC: H01L21/02 ,  B08B3/08 ,  H01L21/67

Abstract: According to an embodiment, the substrate treatment device includes a dilutor configured to dilute a first liquid containing a metal ion and exhibiting acidity. The device further includes a pH changer configured to change a pH of the first liquid before or after being diluted by the dilutor. The device further includes a substrate conditioner configured to treat the substrate using the first liquid, which is diluted by the dilutor and with the pH changed by the pH changer.

公开(公告)号：US20180261529A1

公开(公告)日：2018-09-13

申请号：US15698328

申请日：2017-09-07

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito YOSHIMIZU ,  Yoshiro Shimojo ,  Shinya Arai

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L23/481 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/5226 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

公开(公告)号：US20200211864A1

公开(公告)日：2020-07-02

申请号：US16556014

申请日：2019-08-29

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yasuhito YOSHIMIZU ,  Hakuba KITAGAWA ,  Takaumi MORITA

IPC: H01L21/67 ,  H01L21/445 ,  H01L21/673

Abstract: According to one embodiment, a substrate processing apparatus includes a table configured to place a substrate thereon and to connect the substrate to a positive electrode, an counter electrode located opposite to the table, having a plurality of holes, and connected to a negative electrode, and a holding unit located opposite to the table across the counter electrode and configured to supply a chemical liquid to the counter electrode while holding the counter electrode.

公开(公告)号：US20200066550A1

公开(公告)日：2020-02-27

申请号：US16278757

申请日：2019-02-19

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hakuba KITAGAWA ,  Yasuhito YOSHIMIZU ,  Fuyuma ITO ,  Hiroyuki TANIZAKI

IPC: H01L21/67 ,  H01L21/3213

Abstract: In one embodiment, a substrate treatment apparatus includes a supporter configured to support and rotate a substrate, and a liquid supplier configured to supply a liquid to the substrate. The apparatus further includes a wall provided separately from the supporter and at least partially surrounding the supporter, and a detector provided between the supporter and the wall and configured to detect a change in the liquid.

公开(公告)号：US20190259777A1

公开(公告)日：2019-08-22

申请号：US16398386

申请日：2019-04-30

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yasuhito YOSHIMIZU ,  Akifumi GAWASE ,  Kei WATANABE ,  Shinya ARAI

IPC: H01L27/11582 ,  H01L21/764

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a second air gap, a first insulating film, a semiconductor film, and a stacked film. The stacked body is provided above the substrate and includes a plurality of electrode films stacked via a first air gap. The second air gap extends in a stacking direction of the stacked body. The second air gap separates the stacked body in a first direction crossing the stacking direction. The first insulating film is provided above the stacked body and covers an upper end of the second air gap. The stacked film is provided between a side surface of the electrode film and a side surface of the semiconductor film opposed to the side surface of the electrode film. The stacked film is in contact with the side surface of the electrode film and the side surface of the semiconductor film.

公开(公告)号：US20190088712A1

公开(公告)日：2019-03-21

申请号：US15917145

申请日：2018-03-09

Applicant: Toshiba Memory Corporation

Inventor： Masaki KADO ,  Tsuyoshi KONDO ,  Yasuaki OOTERA ,  Takuya SHIMADA ,  Michael Arnaud QUINSAT ,  Nobuyuki UMETSU ,  Susumu HASHIMOTO ,  Shiho NAKAMURA ,  Hideaki AOCHI ,  Tomoya SANUKI ,  Shinji MIYANO ,  Yoshihiro UEDA ,  Yuichi ITO ,  Yasuhito YOSHIMIZU

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first magnetic layer, and a first nonmagnetic layer. The first magnetic member includes a first extension portion and a third portion. The first extension portion extends along a first direction and includes a first portion and a second portion. The third portion is connected to the second portion. A direction from the first portion toward the second portion is aligned with the first direction. At least a portion of the third portion is tilted with respect to the first direction. The first nonmagnetic layer is provided between the first magnetic layer and the at least a portion of the third portion. The first nonmagnetic layer is provided along the at least a portion of the third portion and is tilted with respect to the first direction.

公开(公告)号：US20180265989A1

公开(公告)日：2018-09-20

申请号：US15700694

申请日：2017-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yasuhito YOSHIMIZU ,  Yuya AKEBOSHI ,  Fuyuma ITO ,  Hakuba KITAGAWA

IPC: C23F1/32 ,  C23F1/08

CPC classification number: C23F1/32 ,  C23F1/02 ,  C23F1/08 ,  C23F1/38 ,  C23F1/40

Abstract: According to an embodiment, a substrate treatment apparatus includes a noble metal-containing member having a concave-convex surface including a noble metal, and a liquid chemical supply member to supply a liquid chemical. While convex portions of the concave-convex surface are contact with a predetermined surface of a metal, the liquid chemical is supplied onto the surface of the metal to remove the metal with etching.

公开(公告)号：US20180082893A1

公开(公告)日：2018-03-22

申请号：US15449233

申请日：2017-03-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fuyuma ITO ,  Yasuhito YOSHIMIZU ,  Yuya AKEBOSHI ,  Hisashi OKUCHI ,  Masayuki KITAMURA

IPC: H01L21/768 ,  H01L21/027 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/0272 ,  H01L21/0273 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238

Abstract: According to some embodiments, a semiconductor device manufacturing method includes forming a sacrificial film on a material film. The method includes processing the sacrificial film, and forming a first groove in the sacrificial film having a first width and a second groove in the sacrificial film having a second width larger than the first width, the material film defining a base of the first groove and a base of the second groove. The method includes forming a catalyst layer on the sacrificial film, and on the base of the first groove and the base of the second groove. The method includes forming a first metal film having a thickness equal to or larger than half the first width and smaller than half the second width on the catalyst layer by plating. The method includes removing at least a portion of the first metal film in the second groove while leaving a portion of the first metal film in the first groove unremoved. The method includes removing the catalyst layer on the sacrificial film while leaving the catalyst layer on the base of the second groove unremoved. The method includes forming a second metal film in the second groove by the plating.