公开(公告)号：US10157998B2

公开(公告)日：2018-12-18

申请号：US15811374

申请日：2017-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Da-Yuan Lee ,  Hsin-Yi Lee ,  Kuan-Ting Liu

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

Abstract: A field effect transistor includes a channel layer made of a semiconductor and a metal gate structure. The metal gate structure includes a gate dielectric layer, a barrier layer formed on the gate dielectric layer, a work function adjustment layer formed on the barrier layer and made of one of Al and TiAl, a blocking layer formed on the work function adjustment layer and made of TiN, and a body metal layer formed on the blocking layer and made of W. A gate length over the channel layer is in a range from 5 nm to 15 nm, and a thickness of the first conductive layer is in a range of 0.2 nm to 3.0 nm. A range between a largest thickness and a smallest thickness of the first conductive layer is more than 0% and less than 10% of an average thickness of the first conductive layer.

公开(公告)号：US10147799B2

公开(公告)日：2018-12-04

申请号：US15074991

申请日：2016-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Cheng Hung ,  Yu-Sheng Wang ,  Weng-Cheng Chen ,  Hao-Han Wei ,  Ming-Ching Chung ,  Chi-Cherng Jeng

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/49 ,  H01L29/40 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238

Abstract: A method of fabricating tantalum nitride barrier layer in an ultra low threshold voltage semiconductor device is provided. The method includes forming a high-k dielectric layer over a semiconductor substrate. Subsequently, a tantalum nitride barrier layer is formed on the high-k dielectric layer. The tantalum nitride barrier layer has a Ta:N ratio between 1.2 and 3. Next, a plurality of first metal gates is formed on the tantalum nitride barrier layer. The first metal gates are patterned, and then a second metal gate is formed on the tantalum nitride barrier layer.

公开(公告)号：US20240363409A1

公开(公告)日：2024-10-31

申请号：US18771313

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chen-Yuan Kao ,  Yi-Wei Chiu ,  Liang-Yueh Ou Yang ,  Yueh-Ching Pai

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/288 ,  H01L23/485 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/2885 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L29/41775 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/7833 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L23/485

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

公开(公告)号：US12021147B2

公开(公告)日：2024-06-25

申请号：US18064350

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chia-Ching Lee ,  Chung-Chiang Wu ,  Ching-Hwanq Su

IPC: H01L21/768 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/7851 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

公开(公告)号：US11616132B2

公开(公告)日：2023-03-28

申请号：US17340802

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chia-Ching Lee ,  Ching-Hwanq Su

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L29/51

Abstract: A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.

公开(公告)号：US11158509B2

公开(公告)日：2021-10-26

申请号：US16877755

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Chi-Cheng Hung ,  Chin-Hsiang Lin ,  Chien-Wei Wang ,  Ching-Yu Chang ,  Chih-Yuan Ting ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yuan-Hsiang Lung ,  Yen-Ming Chen ,  Yung-Sung Yen

IPC: H01L21/265 ,  H01L21/311 ,  H01L21/033

Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.

公开(公告)号：US10658184B2

公开(公告)日：2020-05-19

申请号：US15474522

申请日：2017-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Chi-Cheng Hung ,  Chin-Hsiang Lin ,  Chien-Wei Wang ,  Ching-Yu Chang ,  Chih-Yuan Ting ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yuan-Hsiang Lung ,  Yen-Ming Chen ,  Yung-Sung Yen

IPC: H01L21/265 ,  H01L21/311 ,  H01L21/033

Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.

公开(公告)号：US12068197B2

公开(公告)日：2024-08-20

申请号：US17234136

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chen-Yuan Kao ,  Yi-Wei Chiu ,  Liang-Yueh Ou Yang ,  Yueh-Ching Pai

IPC: H01L21/768 ,  H01L21/288 ,  H01L23/485 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285

CPC classification number: H01L21/76895 ,  H01L21/2885 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L29/41775 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/7833 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L23/485

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

公开(公告)号：US11670690B2

公开(公告)日：2023-06-06

申请号：US16926671

申请日：2020-07-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Cheng Hung ,  Kei-Wei Chen ,  Yu-Sheng Wang ,  Ming-Ching Chung ,  Chia-Yang Wu

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L29/49

CPC classification number: H01L29/41725 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/4966

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first source/drain region, a second source/drain region, first source/drain contact and a first dielectric spacer liner. The gate structure is over the semiconductor substrate. The first source/drain region and the second source/drain region are in the semiconductor substrate and respectively on opposite sides of the gate structure. The first source/drain contact is over the first source/drain region. The first dielectric spacer liner lines a sidewall of the first source/drain contact and extends into the first source/drain region.

公开(公告)号：US11043573B2

公开(公告)日：2021-06-22

申请号：US16176214

申请日：2018-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Cheng Hung ,  Yu-Sheng Wang ,  Weng-Cheng Chen ,  Hao-Han Wei ,  Ming-Ching Chung ,  Chi-Cherng Jeng

IPC: H01L29/51 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238

Abstract: A method of fabricating tantalum nitride barrier layer in an ultra low threshold voltage semiconductor device is provided. The method includes forming a high-k dielectric layer over a semiconductor substrate. Subsequently, a tantalum nitride barrier layer is formed on the high-k dielectric layer. The tantalum nitride barrier layer has a Ta:N ratio between 1.2 and 3. Next, a plurality of first metal gates is formed on the tantalum nitride barrier layer. The first metal gates are patterned, and then a second metal gate is formed on the tantalum nitride barrier layer.