中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

52 records (took 0.022 seconds)

    Memory cell array including a write-assist circuit and embedded coupling capacitor and method of forming same
    12.
    发明授权
    Memory cell array including a write-assist circuit and embedded coupling capacitor and method of forming same 有权
    包括写辅助电路和嵌入式耦合电容器的存储单元阵列及其形成方法

    公开(公告)号：US09281311B2

    公开(公告)日：2016-03-08

    申请号：US14031057

    申请日：2013-09-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ching-Wei Wu ,  Wei-Shuo Kao ,  Chia-Cheng Chen ,  Kuang Ting Chen

    IPC: H01L27/108 ,  H01L29/94 ,  H01L27/11 ,  G11C7/12 ,  G11C7/18 ,  G11C11/419 ,  G11C11/412

    CPC classification number: H01L27/1116 ,  G11C7/12 ,  G11C7/18 ,  G11C11/412 ,  G11C11/419 ,  G11C2207/005 ,  H01L29/94

    Abstract: An integrated circuit includes a plurality of metal layers of bit cells of a memory cell array disposed in a first metal layer and extending in a first direction, a plurality of word lines of the memory cell array disposed in a second metal layer and extending in a second direction that is different from the first direction, and at least two conductive traces disposed in a third metal layer substantially adjacent to each other and extending at least partially across the memory cell array, a first one of the at least two conductive traces coupled to a driving source node of a write assist circuit, and a second conductive trace of the at least two conductive traces coupled to an enable input of the write-assist circuit, where the at least two conductive traces form at least one embedded capacitor having a capacitive coupling to the bit line.

    Abstract translation: 一种集成电路包括设置在第一金属层中并沿第一方向延伸的存储单元阵列的位单元的多个金属层，所述存储单元阵列的多个字线设置在第二金属层中并在 与第一方向不同的第二方向，以及布置在基本上彼此相邻并且至少部分地跨过存储单元阵列延伸的第三金属层中的至少两个导电迹线，所述至少两个导电迹线中的第一导电迹线耦合到 写辅助电路的驱动源节点和耦合到写辅助电路的使能输入的至少两个导电迹线的第二导电迹线，其中所述至少两个导电迹线形成至少一个嵌入式电容器，其具有电容 耦合到位线。

    Semiconductor device and method of manufacture
    15.
    发明授权
    Semiconductor device and method of manufacture 有权

    公开(公告)号：US12136566B2

    公开(公告)日：2024-11-05

    申请号：US17969396

    申请日：2022-10-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

    Semiconductor Device and Method of Manufacture
    18.
    发明申请
    Semiconductor Device and Method of Manufacture 有权

    公开(公告)号：US20230041753A1

    公开(公告)日：2023-02-09

    申请号：US17969396

    申请日：2022-10-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

    Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

Patent Agency Ranking