公开(公告)号：US10002969B2

公开(公告)日：2018-06-19

申请号：US15407839

申请日：2017-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Chih Chieh Yeh ,  Cheng-Hsien Wu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/24 ,  H01L29/267 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/78618 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/78696

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire extends into the source/drain region. The semiconductor wire in the source/drain regions is wrapped around by a second semiconductor material.

公开(公告)号：US09698060B2

公开(公告)日：2017-07-04

申请号：US15005424

申请日：2016-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih Chieh Yeh ,  Chih-Sheng Chang ,  Clement Hsingjen Wann

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8256 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/08

CPC classification number: H01L21/8256 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/6681 ,  H01L29/7848

Abstract: An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.

公开(公告)号：US20160155668A1

公开(公告)日：2016-06-02

申请号：US15005424

申请日：2016-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih Chieh Yeh ,  Chih-Sheng Chang ,  Clement Hsingjen Wann

IPC: H01L21/8256 ,  H01L29/08 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/8256 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/6681 ,  H01L29/7848

Abstract: An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.

Abstract translation: 集成电路结构包括n型鳍式场效应晶体管（FinFET）和p型FinFET。 n型FinFET包括在衬底上的第一锗鳍; 顶表面上的第一栅电介质和第一锗鳍的侧壁; 以及在第一栅极电介质上的第一栅电极。 p型FinFET在衬底上包括第二个锗鳍; 在顶表面上的第二栅电介质和第二锗鳍的侧壁; 和在第二栅极电介质上的第二栅电极。 第一栅电极和第二栅极由具有接近锗的固有能级的功函数的相同材料形成。

公开(公告)号：US20240258301A1

公开(公告)日：2024-08-01

申请号：US18623294

申请日：2024-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hung Wang ,  Ming-Shuan Li ,  Chih Chieh Yeh ,  Zi-Ang Su ,  Chia-Ju Chou

IPC: H01L27/02 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0266 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0296 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78696

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate and an epitaxial stack disposed above the semiconductor substrate. The epitaxial stack includes first and second type epitaxial layers, the first and second type epitaxial layers having different material compositions. The first and second type epitaxial layers are alternatingly disposed in a vertical direction. The semiconductor device also includes a first doped region in the epitaxial stack and a second doped region in the epitaxial stack. The first doped region has a first dopant of a first conductivity type. The second doped region has a second dopant of a second conductivity type opposite the first conductivity type. The semiconductor device also includes first and second gate stacks disposed above the epitaxial stack. A portion of the first doped region and a portion of the second doped region are between the first and second gate stacks.

公开(公告)号：US11798989B2

公开(公告)日：2023-10-24

申请号：US17805719

申请日：2022-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Peng ,  Hung-Li Chiang ,  Yu-Lin Yang ,  Chih Chieh Yeh ,  Yee-Chia Yeo ,  Chi-Wen Liu

IPC: H01L29/06 ,  H01L21/82 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/786 ,  H01L21/306 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L21/3065

CPC classification number: H01L29/0673 ,  H01L21/3081 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696 ,  H01L21/3065

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

公开(公告)号：US20230326802A1

公开(公告)日：2023-10-12

申请号：US18329396

申请日：2023-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Chi Yang ,  Allen Chien ,  Tsai-Yu Huang ,  Chien-Chih Lin ,  Po-Kai Hsiao ,  Shih-Hao Lin ,  Chien-Chih Lee ,  Chih Chieh Yeh ,  Cheng-Ting Ding ,  Tsung-Hung Lee

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L29/0607 ,  H01L21/823418 ,  H01L21/823412 ,  H01L29/1054

Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

公开(公告)号：US11652141B2

公开(公告)日：2023-05-16

申请号：US17656258

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Peng ,  Hung-Li Chiang ,  Yu-Lin Yang ,  Chih Chieh Yeh ,  Yee-Chia Yeo ,  Chi-Wen Liu

IPC: H01L21/82 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/786 ,  H01L21/306 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L21/3065

CPC classification number: H01L29/0673 ,  H01L21/3081 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696 ,  H01L21/3065

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material may be be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

公开(公告)号：US11239367B2

公开(公告)日：2022-02-01

申请号：US16914831

申请日：2020-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Chih Chieh Yeh ,  Cheng-Hsien Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.

公开(公告)号：US10804367B2

公开(公告)日：2020-10-13

申请号：US15719686

申请日：2017-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Wei-Sheng Yun ,  I-Sheng Chen ,  Shao-Ming Yu ,  Tzu-Chiang Chen ,  Chih Chieh Yeh

IPC: H01L29/165 ,  H01L21/8236 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66 ,  H01L29/10 ,  H01L27/06 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/40

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

公开(公告)号：US10727110B2

公开(公告)日：2020-07-28

申请号：US16594312

申请日：2019-10-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hsuan Hsiao ,  Yee-Chia Yeo ,  Tung Ying Lee ,  Chih Chieh Yeh

IPC: H01L29/417 ,  H01L21/768 ,  H01L27/088 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/78

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.