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    PATTERNING APPROACH FOR IMPROVED VIA LANDING PROFILE
    14.
    发明申请
    PATTERNING APPROACH FOR IMPROVED VIA LANDING PROFILE 有权

    公开(公告)号：US20210074636A1

    公开(公告)日：2021-03-11

    申请号：US16952345

    申请日：2020-11-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Yuan Ting ,  Chung-Wen Wu

    IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

    Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.

    Interconnect Structure and Method of Forming the Same
    15.
    发明申请
    Interconnect Structure and Method of Forming the Same 审中-公开

    公开(公告)号：US20200286779A1

    公开(公告)日：2020-09-10

    申请号：US16883095

    申请日：2020-05-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jeng-Shiou Chen ,  Chih-Yuan Ting

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.

    Patterning approach for improved via landing profile
    18.
    发明授权
    Patterning approach for improved via landing profile 有权
    用于通过着陆简档改进的图案化方法

    公开(公告)号：US09312222B2

    公开(公告)日：2016-04-12

    申请号：US13794999

    申请日：2013-03-12

    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

    Inventor： Chih-Yuan Ting ,  Chung-Wen Wu

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

    CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

    Abstract translation: 本公开涉及一种半导体结构及其制造方法，其中间隔元件邻近嵌入在第一互连层的第一电介质层中的金属体形成。 相对于金属体的边缘不对准的通孔形成在第二互连层中的第二介电材料中，第二互连层设置在第一互连层上并且填充有电耦合到金属体的导电材料。 该方法允许形成互连结构，而不会遇到通过第一互连层的电介质材料中的子结构缺陷所呈现的各种问题，以及消除常规间隙填充金属化问题。

    Method for manufacturing semiconductor structure
    19.
    发明授权
    Method for manufacturing semiconductor structure 有权

    公开(公告)号：US11355642B2

    公开(公告)日：2022-06-07

    申请号：US16657035

    申请日：2019-10-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ju-Wang Hsu ,  Chih-Yuan Ting ,  Tang-Xuan Zhong ,  Yi-Nien Su ,  Jang-Shiang Tsai

    IPC: H01L21/00 ,  H01L21/84 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

    Abstract: Methods for manufacturing semiconductor structures are provided. The method includes forming a first masking layer over a substrate and forming a second masking layer over the first masking layer. The method includes forming a photoresist pattern over the second masking layer and patterning the second masking layer through the photoresist pattern. The method further includes diminishing the photoresist pattern and patterning the second masking layer and the first masking layer through the diminished photoresist pattern. The method further includes removing the diminished photoresist pattern and patterning the semiconductor substrate through the second masking layer and the first masking layer to form a fin structure. The method further includes forming a gate structure over the fin structure.

    Integrated circuit
    20.
    发明授权
    Integrated circuit 有权

    公开(公告)号：US11271150B2

    公开(公告)日：2022-03-08

    申请号：US16866114

    申请日：2020-05-04

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tai-Yen Peng ,  Chien-Chung Huang ,  Yu-Shu Chen ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Han-Ting Lin ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Hui-Hsien Wei

    IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

    Abstract: An integrated circuit is provided. The integrated circuit includes a metallization pattern, a dielectric layer, and plural memory devices. The metallization pattern has plural first conductive features and a second conductive feature. The dielectric layer is over the metallization pattern, in which the dielectric layer has a first portion over the first conductive features and a second portion over the second conductive feature. The memory devices are at least partially in the first portion of the dielectric layer and respectively connected with the first conductive features. The first portion of the dielectric layer has a plurality of side parts respectively surrounding the memory devices and an extending part connecting the side parts to each other, and a thickness of the second portion is greater than a thickness of the extending part of the first portion of the dielectric layer.

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