公开(公告)号：US20180292752A1

公开(公告)日：2018-10-11

申请号：US15480976

申请日：2017-04-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Po YANG ,  Chien-Wei WANG ,  Wei-Han LAI ,  Chin-Hsiang LIN

IPC: G03F7/075 ,  H01L21/027 ,  H01L21/311 ,  G03F7/11 ,  G03F7/16 ,  G03F7/38 ,  G03F7/038 ,  G03F7/32 ,  G03F7/20

CPC classification number: H01L21/31144 ,  G03F7/0752 ,  G03F7/405 ,  H01L21/0273

Abstract: Methods for forming a semiconductor structure are provided. The method for forming a semiconductor structure includes forming a material layer over a substrate and forming a resist layer over the material layer. The method for forming a semiconductor structure further includes exposing the resist layer to form an exposed portion of the resist layer and forming a treating material layer over the exposed portion and an unexposed portion of the resist layer. In addition, a top surface of the exposed portion of the resist layer reacts with the treating material layer. The method for forming a semiconductor structure further includes removing the treating material layer and removing the unexposed portion of the resist layer to form an opening in the resist layer after the treating material is removed.

公开(公告)号：US20180177055A1

公开(公告)日：2018-06-21

申请号：US15621646

申请日：2017-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan Wang ,  Cheng-Han WU ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: H05K3/06 ,  G03F7/09 ,  H01L21/027 ,  G03F7/00 ,  G03F7/20

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate. The patterned resist layer has a first pattern width, and the patterned resist layer has a first pattern profile having a first proportion of active sites. In some examples, the patterned resist layer is coated with a treatment material. In some embodiments, the treatment material bonds to surfaces of the patterned resist layer to provide a treated patterned resist layer having a second pattern profile with a second proportion of active sites greater than the first proportion of active sites. By way of example, and as part of the coating the patterned resist layer with the treatment material, a first pattern shrinkage process may be performed, where the treated patterned resist layer has a second pattern width less than a first pattern width.

公开(公告)号：US20180174830A1

公开(公告)日：2018-06-21

申请号：US15628355

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan WANG ,  Cheng-Han WU ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: H01L21/027 ,  H01L21/033 ,  G03F7/20 ,  H01L21/308 ,  H01L21/311

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate, where the patterned resist layer has a first line width roughness. In various embodiments, the patterned resist layer is coated with a treatment material, where a first portion of the treatment material bonds to surfaces of the patterned resist layer. In some embodiments, a second portion of the treatment material (e.g., not bonded to surfaces of the patterned resist layer) is removed, thereby providing a treated patterned resist layer, where the treated patterned resist layer has a second line width roughness less than the first line width roughness.

公开(公告)号：US20180138050A1

公开(公告)日：2018-05-17

申请号：US15352218

申请日：2016-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yang LIN ,  Ming-Hui WENG ,  Cheng-Han WU ,  Chin-Hsiang LIN

IPC: H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/06 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0274 ,  H01L21/0276 ,  H01L21/31055

Abstract: Topographic planarization methods for a lithography process are provided. The method includes providing a substrate having a topography surface. A planarization stack is formed over the topography surface of the substrate. The optical material stack includes a first optical material layer and an overlying second optical material layer, and the first optical material layer has a higher etching rate than the second optical material layer with respect to an etchant. The planarization stack is etched using the etchant to entirely remove the second optical material layer and partially remove the first optical material layer, such that the remaining first optical material layer has a substantially planar surface over the topography surface of the substrate.

公开(公告)号：US20180138034A1

公开(公告)日：2018-05-17

申请号：US15352118

申请日：2016-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Yen LIN ,  Ching-Yu CHANG ,  Kuei-Shun CHEN ,  Chin-Hsiang LIN

IPC: H01L21/027 ,  H01L21/311 ,  G03F7/09 ,  G03F7/004 ,  G03F7/16 ,  G03F7/038 ,  G03F7/20 ,  G03F7/32

CPC classification number: H01L21/0273 ,  G03F7/0045 ,  G03F7/038 ,  G03F7/0382 ,  G03F7/091 ,  G03F7/094 ,  G03F7/162 ,  G03F7/168 ,  G03F7/2002 ,  G03F7/322 ,  G03F7/325 ,  H01L21/02203 ,  H01L21/0332 ,  H01L21/266 ,  H01L21/3081 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144

Abstract: Formation methods of a semiconductor device structure are provided. The method includes forming an under layer over a substrate, forming a middle layer over the under layer, and forming a patterned upper layer over the middle layer. The patterned upper layer has a first opening exposing a portion of the middle layer. The method also includes etching the portion of the middle layer exposed by the first opening to form a second opening exposing a portion of the under layer, and etching the portion of the under layer exposed by the second opening of the middle layer. The method further includes forming pores in the middle layer before or during the etching of the portion of the under layer.

公开(公告)号：US20250147424A1

公开(公告)日：2025-05-08

申请号：US19011395

申请日：2025-01-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hui WENG ,  Chen-Yu LIU ,  Cheng-Han WU ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/40 ,  G03F1/82 ,  G03F7/00 ,  G03F7/30 ,  G03F7/32

Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

公开(公告)号：US20240103375A1

公开(公告)日：2024-03-28

申请号：US18523826

申请日：2023-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chih HO ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/36 ,  H01L21/027

CPC classification number: G03F7/36 ,  H01L21/0274

Abstract: A method of forming a patterned photoresist layer includes the following operations: (i) forming a patterned photoresist on a substrate; (ii) forming a molding layer covering the patterned photoresist; (iii) reflowing the patterned photoresist in the molding layer; and (iv) removing the molding layer from the reflowed patterned photoresist. In some embodiments, the molding layer has a glass transition temperature that is greater than or equal to the glass transition temperature of the patterned photoresist. In yet some embodiments, the molding layer has a glass transition temperature that is 3° C.-30° C. less than the glass transition temperature of the patterned photoresist.

公开(公告)号：US20230236496A1

公开(公告)日：2023-07-27

申请号：US17749675

申请日：2022-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng HSU ,  Huan-Ling LEE ,  Hsin-Chang LEE ,  Chin-Hsiang LIN

IPC: G03F1/64 ,  C01B32/162 ,  C01B32/174

CPC classification number: G03F1/64 ,  C01B32/162 ,  C01B32/174 ,  B82Y40/00

Abstract: A method for forming a pellicle for an extreme ultraviolet lithography is provided. The method includes forming a pellicle membrane over a filter membrane and transferring the pellicle membrane from the filter membrane to a membrane border. Forming the pellicle membrane includes growing carbon nanotubes (CNTs) from in-situ formed metal catalyst particles in a first reaction zone of a reactor, each of the CNTs including a metal catalyst particle at a growing tip thereof, growing boron nitride nanotubes (BNNTs) to surround individual CNTs in a second reaction zone of the reactor downstream of the first reaction zone, thereby forming heterostructure nanotubes each including a CNT core and a BNNT shell, and collecting the heterostructure nanotubes on the filter membrane. The metal catalyst particles are partially or completely removed during growing the BNNTs.

公开(公告)号：US20210311393A1

公开(公告)日：2021-10-07

申请号：US17150317

申请日：2021-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Yang LIN ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/039 ,  G03F7/38 ,  G03F7/40 ,  G03F7/004 ,  G03F7/20 ,  G03F7/32

Abstract: A photoresist composition includes a photoactive compound and a polymer. The polymer has a polymer backbone including one or more groups selected from: The polymer backbone includes at least one group selected from B, C-1, or C-2, wherein ALG is an acid labile group, and X is linking group.

公开(公告)号：US20210200091A1

公开(公告)日：2021-07-01

申请号：US16952023

申请日：2020-11-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chih HO ,  Chin-Hsiang LIN ,  Ching-Yu CHANG

IPC: G03F7/11 ,  C09D183/04 ,  H01L21/027

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist underlayer over a semiconductor substrate. The underlayer includes a polymer having a photocleavable functional group. A photoresist layer is formed over the underlayer. The photoresist layer is selectively exposed to actinic radiation, and the selectively exposed photoresist layer is developed to form a photoresist pattern.