-
11.
公开(公告)号:US20170025381A1
公开(公告)日:2017-01-26
申请号:US14806888
申请日:2015-07-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yu-Cheng Tsai , Chun-Chieh Chuang , Ching-Chun Wang , Dun-Nian Yaung , Feng-Chi Hung , Chih-Hui Huang , Yan-Chih Lu , Ju-Shi Chen
IPC: H01L25/065 , H01L23/528 , H01L23/532 , H01L21/02 , H01L25/00 , H01L21/768 , H01L21/321 , H01L21/311 , H01L23/00 , H01L23/522
CPC classification number: H01L25/0657 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/31111 , H01L21/3212 , H01L21/76807 , H01L21/7684 , H01L21/76843 , H01L21/76871 , H01L21/76877 , H01L21/76883 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L24/80 , H01L24/89 , H01L25/50 , H01L2224/05025 , H01L2224/05147 , H01L2224/08145 , H01L2224/215 , H01L2224/80895 , H01L2224/80896 , H01L2224/94 , H01L2225/06524 , H01L2924/01013 , H01L2924/01022 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028 , H01L2924/0104 , H01L2924/01072 , H01L2224/80
Abstract: An integrated circuit (IC) using a copper-alloy based hybrid bond is provided. The IC comprises a pair of semiconductor structures vertically stacked upon one another. The pair of semiconductor structures comprise corresponding dielectric layers and corresponding metal features arranged in the dielectric layers. The metal features comprise a copper alloy having copper and a secondary metal. The IC further comprises a hybrid bond arranged at an interface between the semiconductor structures. The hybrid bond comprises a first bond bonding the dielectric layers together and a second bond bonding the metal features together. The second bond comprises voids arranged between copper grains of the metal features and filled by the secondary metal. A method for bonding a pair of semiconductor structures together using the copper-alloy based hybrid bond is also provided.
Abstract translation: 提供了使用基于铜合金的混合键的集成电路(IC)。 IC包括彼此垂直堆叠的一对半导体结构。 该对半导体结构包括布置在电介质层中的对应介电层和相应的金属特征。 金属特征包括具有铜和二次金属的铜合金。 IC还包括布置在半导体结构之间的界面处的混合键。 混合键包括将电介质层结合在一起的第一键和将金属特征粘合在一起的第二键。 第二结合包括布置在金属特征的铜颗粒之间并由二次金属填充的空隙。 还提供了使用基于铜合金的混合键将一对半导体结构结合在一起的方法。
-
公开(公告)号:US20230378139A1
公开(公告)日:2023-11-23
申请号:US18359311
申请日:2023-07-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shu-Ting Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Chia-Chieh Lin , U-Ting Chen
IPC: H01L25/065 , H01L25/00 , H01L23/48 , H01L23/00 , H01L21/768 , H01L23/532
CPC classification number: H01L25/0657 , H01L25/50 , H01L23/481 , H01L24/92 , H01L21/76898 , H01L2224/821 , H01L2224/82106 , H01L2224/24145 , H01L21/76831 , H01L2224/9212 , H01L23/53223 , H01L2224/80896 , H01L2224/8203 , H01L24/80 , H01L23/53238 , H01L2224/9202 , H01L24/82 , H01L2924/0002 , H01L21/76805 , H01L2225/06541 , H01L23/53266
Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
-
公开(公告)号:US10886320B2
公开(公告)日:2021-01-05
申请号:US16387989
申请日:2019-04-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wen-I Hsu , Feng-Chi Hung , Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu
IPC: H01L27/146
Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.
-
公开(公告)号:US20190244999A1
公开(公告)日:2019-08-08
申请号:US16388071
申请日:2019-04-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wen-De Wang , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Jeng-Shyan Lin
IPC: H01L27/146 , H01L23/48
CPC classification number: H01L27/14636 , H01L23/481 , H01L27/14621 , H01L27/1464 , H01L27/14683
Abstract: An image sensor device includes a pixel array, a control circuit, an interconnect structure, and a conductive layer. The pixel array is disposed on a device substrate within a pixel region. The control circuit disposed on the device substrate within a circuit region, the control circuit being adjacent and electrically coupled to the pixel array. The interconnect structure overlies and electrically connects the control circuit and the pixel array. The interconnect structure includes interconnect metal layers separated from each other by inter-metal dielectric layers and vias that electrically connect between metal traces of the interconnect layers. The conductive layer disposed over the interconnect structure and electrically connected to the interconnect structure by an upper via disposed through an upper inter-metal dielectric layer therebetween. The conductive layer extends laterally within outermost edges of the interconnect structure and within the pixel region and the circuit region.
-
公开(公告)号:US20190221548A1
公开(公告)日:2019-07-18
申请号:US16367720
申请日:2019-03-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Sin-Yao Huang , Chun-Chieh Chuang , Ching-Chun Wang , Sheng-Chau Chen , Dun-Nian Yaung , Feng-Chi Hung , Yung-Lung Lin
IPC: H01L25/065 , H01L25/00 , H01L27/146 , H01L23/00 , H01L23/498
CPC classification number: H01L25/0657 , H01L23/49838 , H01L23/52 , H01L24/00 , H01L24/05 , H01L25/50 , H01L27/14634 , H01L27/14636 , H01L2225/06513 , H01L2225/06544
Abstract: In some embodiments, the present disclosure relates to a method of forming a multi-dimensional integrated chip. The method includes forming a first plurality of interconnect layers within a first dielectric structure on a front-side of a first substrate and forming a second plurality of interconnect layers within a second dielectric structure on a front-side of a second substrate. A first redistribution layer coupled to the first plurality of interconnect layers is bonded to a second redistribution layer coupled to the second plurality of interconnect layers along an interface. A recess is formed within a back-side of the second substrate and over the second plurality of interconnect layers. A bond pad is formed within the recess. The bond pad is laterally separated from the first redistribution layer by a non-zero distance.
-
公开(公告)号:US09704827B2
公开(公告)日:2017-07-11
申请号:US14750003
申请日:2015-06-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Sin-Yao Huang , Chun-Chieh Chuang , Ching-Chun Wang , Sheng-Chau Chen , Dun-Nian Yaung , Feng-Chi Hung , Yung-Lung Lin
IPC: H01L25/065 , H01L23/498 , H01L25/00 , H01L27/146 , H01L23/52
CPC classification number: H01L25/0657 , H01L23/49838 , H01L23/52 , H01L25/50 , H01L27/14634 , H01L27/14636 , H01L2225/06513 , H01L2225/06544
Abstract: The present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is laterally offset from a back-side bond pad. The multi-dimensional integrated chip has a first integrated chip die with a first plurality of metal interconnect layers disposed within a first inter-level dielectric layer arranged onto a front-side of a first semiconductor substrate. The multi-dimensional integrated chip also has a second integrated chip die with a second plurality of metal interconnect layers disposed within a second inter-level dielectric layer abutting the first ILD layer. A bond pad is disposed within a recess extending through the second semiconductor substrate. A redistribution layer vertically extends between the first plurality of metal interconnect layers and the second plurality of metal interconnect layers at a position that is laterally offset from the bond pad.
-
公开(公告)号:US11804473B2
公开(公告)日:2023-10-31
申请号:US17333120
申请日:2021-05-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Sin-Yao Huang , Chun-Chieh Chuang , Ching-Chun Wang , Sheng-Chau Chen , Dun-Nian Yaung , Feng-Chi Hung , Yung-Lung Lin
IPC: H01L25/00 , H01L25/065 , H01L23/498 , H01L27/146 , H01L23/00 , H01L23/52
CPC classification number: H01L25/0657 , H01L23/49838 , H01L24/00 , H01L25/50 , H01L27/14634 , H01L27/14636 , H01L23/52 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2224/05569 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/08147 , H01L2224/80357 , H01L2224/80815 , H01L2225/06513 , H01L2225/06544 , H01L2224/05647 , H01L2924/00014 , H01L2224/05624 , H01L2924/00014
Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects arranged within a first inter-level dielectric (ILD) structure on a first substrate, and a second plurality of interconnects arranged within a second ILD structure between the first ILD structure and a second substrate. A bonding structure is disposed within a recess extending through the second substrate. A connector structure is vertically between the first plurality of interconnects and the second plurality of interconnects. The second plurality of interconnects include a first interconnect directly contacting the bonding structure. The second plurality of interconnects also include one or more extensions extending from directly below the first interconnect to laterally outside of the first interconnect and directly above the connector structure, as viewed along a cross-sectional view.
-
公开(公告)号:US20230201613A1
公开(公告)日:2023-06-29
申请号:US18178732
申请日:2023-03-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shu-Ting Tsai , Jeng-Shyan Lin , Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung
IPC: A61N1/39 , H01L25/00 , H01L27/06 , H01L27/146 , H01L21/768 , H01L23/48 , H01L23/532
CPC classification number: A61N1/3931 , H01L25/50 , H01L27/0688 , H01L27/14634 , H01L21/76898 , H01L23/481 , H01L23/53238 , A61N1/3987 , H01L2224/80894 , H01L2224/08145 , H01L2224/80896 , H01L2224/9202 , H01L2224/94 , H01L2924/1431 , H01L2225/06513 , H01L2225/06541 , H01L23/53257 , H01L2224/9212
Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.
-
公开(公告)号:US11024602B2
公开(公告)日:2021-06-01
申请号:US16367720
申请日:2019-03-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Sin-Yao Huang , Chun-Chieh Chuang , Ching-Chun Wang , Sheng-Chau Chen , Dun-Nian Yaung , Feng-Chi Hung , Yung-Lung Lin
IPC: H01L25/065 , H01L23/498 , H01L25/00 , H01L27/146 , H01L23/00 , H01L23/52
Abstract: In some embodiments, the present disclosure relates to a method of forming a multi-dimensional integrated chip. The method includes forming a first plurality of interconnect layers within a first dielectric structure on a front-side of a first substrate and forming a second plurality of interconnect layers within a second dielectric structure on a front-side of a second substrate. A first redistribution layer coupled to the first plurality of interconnect layers is bonded to a second redistribution layer coupled to the second plurality of interconnect layers along an interface. A recess is formed within a back-side of the second substrate and over the second plurality of interconnect layers. A bond pad is formed within the recess. The bond pad is laterally separated from the first redistribution layer by a non-zero distance.
-
公开(公告)号:US20200306552A1
公开(公告)日:2020-10-01
申请号:US16901884
申请日:2020-06-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shu-Ting Tsai , Jeng-Shyan Lin , Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung
IPC: A61N1/39 , H01L25/00 , H01L27/06 , H01L27/146 , H01L21/768 , H01L23/48 , H01L23/532
Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.
-
-
-
-
-
-
-
-
-