公开(公告)号：US20230369103A1

公开(公告)日：2023-11-16

申请号：US18359414

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76825 ,  H01L21/76822 ,  H01L23/5283 ,  H01L21/76883 ,  H01L23/53295 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/53242 ,  H01L21/76886

Abstract: A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.

公开(公告)号：US20230223302A1

公开(公告)日：2023-07-13

申请号：US17663302

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Chang-Ting Chung ,  Yi-Hsiang Chao ,  Yu-Ting Wen ,  Kai-Chieh Yang ,  Yu-Chen Ko ,  Peng-Hao Hsu ,  Ya-Yi Cheng ,  Min-Hsiu Hung ,  Chun-Hsien Huang ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/02

CPC classification number: H01L21/76895 ,  H01L23/535 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76889

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

公开(公告)号：US20230155004A1

公开(公告)日：2023-05-18

申请号：US17651721

申请日：2022-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Wen Wu ,  Chun-Hsien Huang ,  Wei-Jung Lin ,  Chih-Wei Chang

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/7851 ,  H01L29/41791 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method includes depositing an inter-layer dielectric (ILD) over a source/drain region; forming a contact opening through the ILD, wherein the contact opening exposes the source/drain region; forming a metal-semiconductor alloy region on the source/drain region; depositing a first layer of a conductive material on the metal-semiconductor alloy region; depositing an isolation material along sidewalls of the contact opening and over the first layer of the conductive material; etching the isolation material to expose the first layer of the conductive material, wherein the isolation material extends along sidewalls of the contact opening after etching the isolation material; and depositing a second layer of the conductive material on the first layer of the conductive material.

公开(公告)号：US20170287779A1

公开(公告)日：2017-10-05

申请号：US15628267

申请日：2017-06-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsien Huang ,  Hong-Mao Lee ,  Hsien-Lung Yang ,  Yu-Kai Chen ,  Wei-Jung Lin

IPC: H01L21/768 ,  H01L21/8238

Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.

公开(公告)号：US09773779B2

公开(公告)日：2017-09-26

申请号：US14856813

申请日：2015-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： I-Tseng Chen ,  Hon-Lin Huang ,  Chun-Hsien Huang ,  Yu-Hung Lin

IPC: H01L21/20 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/02271 ,  H01L21/823437 ,  H01L28/20

Abstract: A semiconductor device structure including a resistor layer is provided. The semiconductor device structure includes a gate structure formed over the first region of the substrate and an inter-layer dielectric (ILD) layer formed adjacent to the gate structure. The semiconductor device structure further includes a resistor layer is formed over the ILD layer over the second region of the substrate, and the major structure of the resistor layer is amorphous.

公开(公告)号：US12288716B2

公开(公告)日：2025-04-29

申请号：US18648979

申请日：2024-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsien Huang ,  I-Li Chen ,  Pin-Wen Chen ,  Yuan-Chen Hsu ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

公开(公告)号：US20240395874A1

公开(公告)日：2024-11-28

申请号：US18787191

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsien Huang ,  Chang-Ting Chung ,  Wei-Cheng Lin ,  Wei-Jung Lin ,  Chih-Wei Chang

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/321 ,  H01L21/768 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

公开(公告)号：US20240332076A1

公开(公告)日：2024-10-03

申请号：US18738443

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yip Loh ,  Chih-Wei Chang ,  Hong-Mao Lee ,  Chun-Hsien Huang ,  Yu-Ming Huang ,  Yan-Ming Tsai ,  Yu-Shiuan Wang ,  Hung-Hsu Chen ,  Yu-Kai Chen ,  Yu-Wen Cheng

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76856 ,  H01L21/76805 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/5226 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L21/28518 ,  H01L29/785

Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.

公开(公告)号：US11791204B2

公开(公告)日：2023-10-17

申请号：US17171210

申请日：2021-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76825 ,  H01L21/76816 ,  H01L21/76822 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53242 ,  H01L23/53295

Abstract: A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.

公开(公告)号：US11652053B2

公开(公告)日：2023-05-16

申请号：US17171320

申请日：2021-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/532 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53242 ,  H01L21/3215 ,  H01L21/76883 ,  H01L23/5226

Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.