Patent search ap:("Taiwan Semiconductor Manufacturing Co. Page Ltd.") AND inv:"Chun-Jen Chen"

11.

发明授权
Package and package-on-package structure having elliptical conductive columns 有权

公开(公告)号：US10573573B2

公开(公告)日：2020-02-25

申请号：US15925790

申请日：2018-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Huan Chiu , Chun-Jen Chen , Chen-Shien Chen , Kuo-Chio Liu , Kuo-Hui Chang , Chung-Yi Lin , Hsi-Kuei Cheng , Yi-Jen Lai

IPC: H01L23/31 , H01L25/065 , H01L25/07 , H01L25/11 , H01L21/56 , H01L23/00 , H01L25/075

Abstract: A package includes a die, a plurality of first conductive structures, a plurality of second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. The first conductive structures include cylindrical columns and the second conductive structures include elliptical columns or conical frustums. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the active surface of the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.

12.

发明申请
PACKAGE, PACKAGE-ON-PACKAGE STRUCTURE, AND METHOD OF MANUFACTURING PACKAGE-ON-PACKAGE STRUCTURE 审中-公开

公开(公告)号：US20190295913A1

公开(公告)日：2019-09-26

申请号：US15925790

申请日：2018-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Huan Chiu , Chun-Jen Chen , Chen-Shien Chen , Kuo-Chio Liu , Kuo-Hui Chang , Chung-Yi Lin , Hsi-Kuei Cheng , Yi-Jen Lai

IPC: H01L23/31 , H01L21/56 , H01L23/00

Abstract: A package includes a die, a plurality of first conductive structures, a plurality of second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. The first conductive structures include cylindrical columns and the second conductive structures include elliptical columns or conical frustums. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the active surface of the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.

13.

发明申请
Image Process Method to Improve Mask Inspection Performance 有权
Title translation: 提高面膜检测性能的图像处理方法

公开(公告)号：US20150154326A1

公开(公告)日：2015-06-04

申请号：US14096167

申请日：2013-12-04

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Meng-Lin Lu , Ching-Ting Yang , Chun-Jen Chen , Chien-Hung Lai , Jong-Yuh Chang

IPC: G06F17/50

CPC classification number: G03F1/84

Abstract: The present disclosure relates to a method of inspecting a photomask to decrease false defects, which uses a plurality of image rendering models with varying emphasis on different design aspects, and an associated apparatus. In some embodiments, the method is performed by forming an integrated circuit (IC) design comprising a graphical representation of an integrated circuit. A first image rendering simulation is performed on the IC design using an initial image rendering model to determine a plurality of initial mask defects. A second image rendering simulation is performed on the IC design using a modified image rendering model that emphasizes a design aspect to determine a plurality of modified mask defects. By comparing the plurality of initial mask defects with the plurality of modified mask defects, falsely identified mask defects can be detected and eliminated.

Abstract translation: 本公开涉及一种检查光掩模以减少错误缺陷的方法，其使用多个不同强调不同设计方面的图像渲染模型以及相关联的装置。在一些实施例中，该方法通过形成包括集成电路的图形表示的集成电路（IC）设计来执行。使用初始图像渲染模型对IC设计执行第一图像渲染模拟以确定多个初始掩模缺陷。使用强调设计方面以确定多个修改的掩模缺陷的修改的图像渲染模型对IC设计执行第二图像渲染模拟。通过将多个初始掩模缺陷与多个修改的掩模缺陷进行比较，可以检测和消除错误识别的掩模缺陷。

14.

发明公开
Shifting Contact Pad for Reducing Stress 审中-公开

公开(公告)号：US20230275047A1

公开(公告)日：2023-08-31

申请号：US17661154

申请日：2022-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jen Chen , Wei-Chun Pai , Cheng Wei Ho , Sheng-Huan Chiu

IPC: H01L23/00

CPC classification number: H01L24/02 , H01L24/05 , H01L24/94 , H01L24/03 , H01L24/13 , H01L2224/02313 , H01L2224/02331 , H01L2224/0235 , H01L2224/02381 , H01L2224/0239 , H01L2224/02373 , H01L2224/02375 , H01L2224/03462 , H01L2224/03464 , H01L24/04 , H01L2224/0401 , H01L2224/05008 , H01L2224/05012 , H01L2224/05015 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05166 , H01L2224/05558 , H01L2224/05564 , H01L2224/05569 , H01L24/06 , H01L2224/06138 , H01L2224/05582 , H01L2224/05647 , H01L24/11 , H01L2224/1146 , H01L2224/13082 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13124 , H01L24/16 , H01L2224/16148 , H01L2224/16227 , H01L2224/16238 , H01L24/81 , H01L2224/81801 , H01L24/32 , H01L2224/32145 , H01L2224/32225 , H01L24/92 , H01L2224/92125 , H01L2224/94

Abstract: A method includes forming a first polymer layer over a plurality of metal pads, and patterning the first polymer layer to forming a plurality of openings in the first polymer layer. The plurality of metal pads are exposed through the plurality of openings. A plurality of conductive vias are formed in the plurality of openings. A plurality of conductive pads are formed over and contacting the plurality of conductive vias. A conductive pad in the plurality of conductive pads is laterally shifted from a conductive via directly underlying, and in physical contact with, the conductive pad. A second polymer layer is formed to cover and in physical contact with the plurality of conductive pads.

15.

发明公开
Integrated Circuit Packages and Methods of Forming the Same 审中-公开

公开(公告)号：US20230245991A1

公开(公告)日：2023-08-03

申请号：US17743086

申请日：2022-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chun-Jen Chen , Wei-Chun Pai , Cheng Wei Ho , Sheng-Huan Chiu

IPC: H01L23/00 , H01L25/065 , H01L23/538

CPC classification number: H01L24/24 , H01L25/0655 , H01L23/5381 , H01L23/5386 , H01L24/19 , H01L23/49816

Abstract: In an embodiment, a device includes: an integrated circuit die including a die connector; a dielectric layer on the integrated circuit die; an under-bump metallurgy layer having a line portion on the dielectric layer and having a via portion extending through the dielectric layer to contact the die connector; a through via on the line portion of the under-bump metallurgy layer, the through via having a first curved sidewall proximate the die connector, the through via having a second curved sidewall distal the die connector, the first curved sidewall having a longer arc length than the second curved sidewall; and an encapsulant around the through via and the under-bump metallurgy layer.

16.

发明授权
Bump structure and method for forming the same 有权

公开(公告)号：US10090267B2

公开(公告)日：2018-10-02

申请号：US14208744

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Li-Guo Lee , Yung-Sheng Liu , Yi-Chen Liu , Yi-Jen Lai , Chun-Jen Chen , Hsi-Kuei Cheng

IPC: H01L23/00

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a modified conductive pillar having a top portion and a bottom portion formed over the metal pad and a solder layer formed over the modified conductive pillar. In addition, the top portion of the modified conductive pillar has a first sidewall in a first direction and a bottom portion of the modified conductive pillar has a second sidewall in a second direction different from the first direction.