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公开(公告)号：US09564448B2
公开(公告)日：2017-02-07
申请号：US14718171
申请日：2015-05-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fu-Ting Sung , Chung-Chiang Min , Wei-Hang Huang , Shih-Chang Liu , Chia-Shiung Tsai
IPC: H01L29/788 , H01L21/283 , H01L27/115 , H01L29/78 , H01L21/28 , H01L29/34 , H01L29/423 , H01L29/66 , H01L23/528 , H01L29/49
CPC classification number: H01L27/11568 , H01L21/28 , H01L21/28273 , H01L21/28282 , H01L21/76805 , H01L23/528 , H01L27/11521 , H01L29/34 , H01L29/42324 , H01L29/4234 , H01L29/4916 , H01L29/66825 , H01L29/7831 , H01L29/788 , H01L29/7881 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device structure further includes a memory gate formed over the substrate and a first spacer formed on a sidewall of the memory gate. The semiconductor device structure further includes a contact formed over the memory gate, wherein a portion of the contact extends into the first spacer.
Abstract translation: 提供半导体器件结构。 半导体器件结构包括衬底和形成在衬底上的控制栅极。 半导体器件结构还包括形成在衬底上的存储器栅极和形成在存储器栅极的侧壁上的第一间隔物。 半导体器件结构还包括形成在存储器栅极上的触点，其中触点的一部分延伸到第一间隔物中。
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公开(公告)号：US20160365512A1
公开(公告)日：2016-12-15
申请号：US14737830
申请日：2015-06-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fu-Ting Sung , Chung-Yen Chou , Shih-Chang Liu
CPC classification number: H01L45/146 , H01L27/2436 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/16 , H01L45/1675
Abstract: The present disclosure relates to integrated circuits having a resistive random access memory (RRAM) cell, and associated methods of forming such RRAM cells. In some embodiments, the RRAM cell includes a bottom electrode and a top electrode which are separated from one another by an RRAM dielectric. A bottom electrode sidewall and a top electrode sidewall are vertically aligned to one another, and an RRAM dielectric sidewall is recessed back from the bottom electrode sidewall and the top electrode sidewall.
Abstract translation: 本公开涉及具有电阻随机存取存储器（RRAM）单元的集成电路以及形成这种RRAM单元的相关方法。 在一些实施例中，RRAM单元包括通过RRAM电介质彼此分离的底部电极和顶部电极。 底部电极侧壁和顶部电极侧壁彼此垂直对准，并且RRAM电介质侧壁从底部电极侧壁和顶部电极侧壁向后凹陷。
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公开(公告)号：US20160268505A1
公开(公告)日：2016-09-15
申请号：US14645878
申请日：2015-03-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fu-Ting Sung , Chang-Ming Wu , Hsai-Wei Chen , Shih-Chang Liu , Wen-Ting Chu , Yu-Wen Liao
CPC classification number: H01L45/1233 , H01L27/2436 , H01L45/08 , H01L45/1253 , H01L45/146 , H01L45/1675
Abstract: The present disclosure relates to an integrated circuits device having a RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect layer surrounded by a lower ILD layer and a bottom electrode disposed over the lower metal interconnect layer. The bottom electrode has a lower portion surrounded by a bottom dielectric layer and an upper portion wider than the lower portion. The bottom dielectric layer is disposed over the lower metal interconnect layer and the lower ILD layer. The integrated circuit device also has a RRAM dielectric with a variable resistance located on the bottom electrode, and a top electrode located over the RRAM dielectric. The integrated circuit device also has a top dielectric layer located over the bottom dielectric layer abutting sidewalls of the upper portion of the bottom electrode, the RRAM dielectric, and the top electrode.
Abstract translation: 本公开涉及具有RRAM单元的集成电路器件和相关联的形成方法。 在一些实施例中，集成电路器件具有由下部ILD层围绕的下部金属互连层和设置在下部金属互连层上的底部电极。 底部电极具有被底部电介质层包围的下部和比下部更宽的上部。 底部介电层设置在下部金属互连层和下部ILD层之上。 集成电路器件还具有位于底部电极上的可变电阻的RRAM电介质，以及位于RRAM电介质上方的顶部电极。 集成电路器件还具有位于底部电介质层上方的顶部电介质层，该电介质层邻接底部电极的上部，RRAM电介质和顶部电极的侧壁。
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公开(公告)号：US09196825B2
公开(公告)日：2015-11-24
申请号：US14016343
申请日：2013-09-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Hang Huang , Fu-Ting Sung , Chern-Yow Hsu , Shih-Chang Liu , Chia-Shiung Tsai
Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
Abstract translation: 集成电路器件包括衬底和磁隧道结（MTJ）。 MTJ至少包括被钉扎层，阻挡层和自由层。 MTJ形成在衬底的表面上。 在被钉扎层，阻挡层和自由层中，自由层首先形成并且最接近表面。 这使得在蚀刻自由层之前，可以在自由层的周边区域上形成间隔物。 由蚀刻或其它自由层边界限定工艺导致的对自由层的任何损伤通过间隔物保持与隧道结一定距离。
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公开(公告)号：US11050021B2
公开(公告)日：2021-06-29
申请号：US16678538
申请日：2019-11-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor： Chern-Yow Hsu , Fu-Ting Sung , Shih-Chang Liu
Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a dielectric layer over the bottom electrode layer. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the dielectric layer and patterning the bottom electrode layer, the dielectric layer, and the top electrode layer to form a dielectric structure between a bottom electrode and a top electrode. The method for manufacturing a semiconductor structure further includes etching the bottom electrode from a sidewall of the bottom electrode to partially expose a bottom surface of the dielectric structure.
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Patent Agency Ranking
公开(公告)号：US20210043832A1
公开(公告)日：2021-02-11
申请号：US17065606
申请日：2020-10-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Hang Huang , Fu-Ting Sung , Chern-Yow Hsu , Shih-Chang Liu , Chia-Shiung Tsai
Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
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公开(公告)号：US10825825B2
公开(公告)日：2020-11-03
申请号：US16510043
申请日：2019-07-12
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Fu-Ting Sung , Chung-Chiang Min , Wei-Hang Huang , Shih-Chang Liu , Chia-Shiung Tsai
IPC: H01L27/11568 , H01L29/78 , H01L21/28 , H01L29/34 , H01L29/423 , H01L29/66 , H01L29/788 , H01L27/11521 , H01L23/528 , H01L29/49 , H01L21/768
Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first gate electrode formed over the substrate. The semiconductor structure further includes a dielectric layer formed on a sidewall of the first gate electrode and a second gate electrode formed over the substrate and separated from the first gate electrode by the dielectric layer. The semiconductor structure further includes a contact formed over the second gate electrode. In addition, the contact has a first extending portion and a second extending portion extending along opposite sidewalls of the second gate electrode.
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公开(公告)号：US10529916B2
公开(公告)日：2020-01-07
申请号：US15463500
申请日：2017-03-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Hang Huang , Fu-Ting Sung , Chern-Yow Hsu , Shih-Chang Liu , Chia-Shiung Tsai
Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
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公开(公告)号：US09806254B2
公开(公告)日：2017-10-31
申请号：US14740101
申请日：2015-06-15
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Fu-Ting Sung , Chern-Yow Hsu , Shih-Chang Liu
IPC: H01L21/311 , H01L45/00 , H01L43/12
CPC classification number: H01L45/08 , H01L43/12 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/16 , H01L45/1675
Abstract: A storage device includes a first electrode, a second electrode, a storage element, a spacer and a barrier structure. The second electrode is opposite to the first electrode. The storage element is disposed between the first electrode and the second electrode. The spacer is formed on a sidewall of the second electrode, and the spacer has a notch positioned on a top surface of the spacer. The barrier structure is embedded in a lateral of the spacer, and the barrier structure has a top extending upwards past a bottom of the notch. In addition, a method of manufacturing the storage device is disclosed as well.
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公开(公告)号：US09543511B2
公开(公告)日：2017-01-10
申请号：US14645878
申请日：2015-03-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fu-Ting Sung , Chang-Ming Wu , Hsia-Wei Chen , Shih-Chang Liu , Wen-Ting Chu , Yu-Wen Liao
CPC classification number: H01L45/1233 , H01L27/2436 , H01L45/08 , H01L45/1253 , H01L45/146 , H01L45/1675
Abstract: The present disclosure relates to an integrated circuits device having a RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect layer surrounded by a lower ILD layer and a bottom electrode disposed over the lower metal interconnect layer. The bottom electrode has a lower portion surrounded by a bottom dielectric layer and an upper portion wider than the lower portion. The bottom dielectric layer is disposed over the lower metal interconnect layer and the lower ILD layer. The integrated circuit device also has a RRAM dielectric with a variable resistance located on the bottom electrode, and a top electrode located over the RRAM dielectric. The integrated circuit device also has a top dielectric layer located over the bottom dielectric layer abutting sidewalls of the upper portion of the bottom electrode, the RRAM dielectric, and the top electrode.
Abstract translation: 本公开涉及具有RRAM单元的集成电路器件和相关联的形成方法。 在一些实施例中，集成电路器件具有由下部ILD层围绕的下部金属互连层和设置在下部金属互连层上的底部电极。 底部电极具有被底部电介质层包围的下部和比下部更宽的上部。 底部介电层设置在下部金属互连层和下部ILD层之上。 集成电路器件还具有位于底部电极上的可变电阻的RRAM电介质，以及位于RRAM电介质上方的顶部电极。 集成电路器件还具有位于底部电介质层上方的顶部电介质层，该电介质层邻接底部电极的上部，RRAM电介质和顶部电极的侧壁。
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