公开(公告)号：US20210098632A1

公开(公告)日：2021-04-01

申请号：US16586790

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Blandine Duriez ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L21/311 ,  H01L21/268 ,  H01L21/285 ,  H01L21/324 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes depositing a light blocking layer along sidewalls and bottom surfaces of the source/drain contact openings and a topmost surface of the at least one dielectric layer. The method further includes performing a laser annealing process to activate dopants in the source/drain contact region. The method further includes forming source/drain contact structures within source/drain contact openings.

公开(公告)号：US10686050B2

公开(公告)日：2020-06-16

申请号：US16415557

申请日：2019-05-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Georgios Vellianitis

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L21/762

Abstract: In a method of manufacturing a semiconductor device, a single crystal oxide layer is formed over a substrate. After the single crystal oxide layer is formed, an isolation structure to define an active region is formed. A gate structure is formed over the single crystal oxide layer in the active region. A source/drain structure is formed.

公开(公告)号：US10332965B2

公开(公告)日：2019-06-25

申请号：US15588804

申请日：2017-05-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Martin Christopher Holland ,  Mark Van Dal ,  Georgios Vellianitis ,  Blandine Duriez ,  Gerben Doornbos

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L29/04 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/40

Abstract: A semiconductor device includes a plurality of fins. Each of the fins has a multi-layer stack comprising a first nanowire and a second nanowire. A first portion of the first nanowire and second nanowire are doped to form source and drain regions. An epitaxial layer wraps around the first portion of first nanowire and second nanowire over the source and drain region. A gate is disposed over a second portion of the first nanowire and second nanowire. The epitaxial layer is interposed in between the first nanowire and the second nanowire over the source and drain region. The epitaxial layer has a zig-zag contour.

公开(公告)号：US09711608B1

公开(公告)日：2017-07-18

申请号：US15173222

申请日：2016-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Blandine Duriez ,  Georgios Vellianitis

IPC: H01L21/338 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/42392 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: In a method of manufacturing a semiconductor device, a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked is formed over a substrate. The stacked structure is formed into a fin structure. A sacrificial gate structure is formed over the fin structure. The part of the fin structure covered by the sacrificial gate structure is a channel region. The first semiconductor layers are melted by applying heat, thereby removing the first semiconductor layers from the channel region and forming a source/drain region made of a material of the first semiconductor. A dielectric layer is formed to cover the source/drain region and the sacrificial gate structure. The sacrificial gate structure is removed to expose the second semiconductor layers in the channel region of the fin structure. A gate dielectric layer and a gate electrode layer are formed around the exposed second semiconductor layers in the channel region.

公开(公告)号：US11848385B2

公开(公告)日：2023-12-19

申请号：US17706199

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Blandine Duriez ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/268 ,  H01L21/285 ,  H01L21/324 ,  H01L21/311

CPC classification number: H01L29/78618 ,  H01L21/268 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78696

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes depositing a light blocking layer along sidewalls and bottom surfaces of the source/drain contact openings and a topmost surface of the at least one dielectric layer. The method further includes performing a laser annealing process to activate dopants in the source/drain contact region. The method further includes forming source/drain contact structures within source/drain contact openings.

公开(公告)号：US11784234B2

公开(公告)日：2023-10-10

申请号：US17813653

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gerben Doornbos ,  Marcus Johannes Henricus van Dal ,  Georgios Vellianitis

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/04 ,  H01L29/207 ,  H10B51/30 ,  H01L29/786 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L29/04 ,  H01L29/207 ,  H01L29/6684 ,  H01L29/7855 ,  H01L29/78648 ,  H10B51/30 ,  H01L2029/7858

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

公开(公告)号：US11721721B2

公开(公告)日：2023-08-08

申请号：US17340240

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Martin Christopher Holland ,  Georgios Vellianitis

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L21/0228 ,  H01L21/02112 ,  H01L21/02271 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/785

Abstract: Provided herein are semiconductor structures that include germanium and have a germanium nitride layer on the surface, as well as methods of forming the same. The described structures include nanowires and fins. Methods of the disclosure include metal-organic chemical vapor deposition with a germanium precursor. The described methods also include using a N2H4 vapor.

公开(公告)号：US11594603B2

公开(公告)日：2023-02-28

申请号：US17162994

申请日：2021-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis ,  Blandine Duriez

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/02 ,  H01L29/423

Abstract: An exemplary device includes a channel layer, a first epitaxial source/drain feature, and a second epitaxial source/drain feature disposed over a substrate. The channel layer is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. A metal gate is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The metal gate is disposed over and physically contacts at least two sides of the channel layer. A source/drain contact is disposed over the first epitaxial source/drain feature. A doped crystalline semiconductor layer, such as a gallium-doped crystalline germanium layer, is disposed between the first epitaxial source/drain feature and the source/drain contact. The doped crystalline semiconductor layer is disposed over and physically contacts at least two sides of the first epitaxial source/drain feature. In some embodiments, the doped crystalline semiconductor layer has a contact resistivity that is less than about 1×10−9 Ω-cm2.

公开(公告)号：US11527552B2

公开(公告)日：2022-12-13

申请号：US17130609

申请日：2020-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Mauricio Manfrini ,  Georgios Vellianitis

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11587 ,  H01L27/11585 ,  H01L29/66 ,  H01L29/51

Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.

公开(公告)号：US20220367666A1

公开(公告)日：2022-11-17

申请号：US17873825

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus van Dal ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate electrode, a ferroelectric insulating layer over the first gate electrode, a semiconductor member over the ferroelectric insulating layer, a gate dielectric layer over the semiconductor member, and a second gate electrode over the gate dielectric layer.