公开(公告)号：US20230154750A1

公开(公告)日：2023-05-18

申请号：US17674575

申请日：2022-02-17

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Chih-Cheng Liu ,  Yi-Chen Kuo ,  Yen-Yu Chen ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/027 ,  G03F7/40

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/0276 ,  G03F7/405

Abstract: Photoresists and methods of forming and using the same are disclosed. In an embodiment, a method includes spin-on coating a first hard mask layer over a target layer; depositing a photoresist layer over the first hard mask layer using chemical vapor deposition or atomic layer deposition, the photoresist layer being deposited using one or more organometallic precursors; heating the photoresist layer to cause cross-linking between the one or more organometallic precursors; exposing the photoresist layer to patterned energy; heating the photoresist layer to cause de-crosslinking in the photoresist layer forming a de-crosslinked portion of the photoresist layer; and removing the de-crosslinked portion of the photoresist layer.

公开(公告)号：US11532507B2

公开(公告)日：2022-12-20

申请号：US17169989

申请日：2021-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han Chen ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chung-Ting Ko ,  Jr-Hung Li ,  Chi On Chui

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/08

Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.

公开(公告)号：US20220123115A1

公开(公告)日：2022-04-21

申请号：US17193626

申请日：2021-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L23/535

Abstract: A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.

公开(公告)号：US20210091191A1

公开(公告)日：2021-03-25

申请号：US16805841

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Jung Ho ,  Jr-Hung Li ,  Tze-Liang Lee ,  Pei-Yu Chou ,  Chi-Ta Lee

IPC: H01L29/417 ,  H01L29/08 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78

Abstract: A field effect transistor includes a semiconductor substrate, source and drain regions, lower source and drain contacts, a metal gate, a first interlayer dielectric layer, a capping layer, and an etch stop layer. The source and drain regions are disposed on the semiconductor substrate. The lower source and drain contacts are disposed on the source and drain regions. The metal gate is disposed in between the lower source and drain contacts. The first interlayer dielectric layer encircles the metal gate and the lower source and drain contacts. The capping layer is disposed on the metal gate. The etch stop layer extends on the first interlayer dielectric layer. An etching selectivity for the etch stop layer over the capping layer is greater than 10.

公开(公告)号：US10483168B2

公开(公告)日：2019-11-19

申请号：US15833912

申请日：2017-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78

Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

公开(公告)号：US10468529B2

公开(公告)日：2019-11-05

申请号：US15646386

申请日：2017-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Bo-Cyuan Lu ,  Jr-Hung Li ,  Chi-On Chui

IPC: H01L21/02 ,  H01L29/78 ,  H01L23/535 ,  H01L29/04 ,  H01L29/165 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/51

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a gate structure over the substrate and having a sidewall, a spacer element over the sidewall of the gate structure and a source/drain portion adjacent to the spacer element and the gate structure. The semiconductor device structure also includes an etch stop layer over the source/drain portion, an interlayer dielectric layer over the etch stop layer and in contact with the spacer element, and a contact plug penetrating through the interlayer dielectric layer and the etch stop layer, and electrically connected to the source/drain portion.

公开(公告)号：US20190148239A1

公开(公告)日：2019-05-16

申请号：US16203814

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423

Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

公开(公告)号：US11822237B2

公开(公告)日：2023-11-21

申请号：US17071004

申请日：2020-10-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hui Weng ,  Chen-Yu Liu ,  Chih-Cheng Liu ,  Yi-Chen Kuo ,  Jia-Lin Wei ,  Yen-Yu Chen ,  Jr-Hung Li ,  Yahru Cheng ,  Chi-Ming Yang ,  Tze-Liang Lee ,  Ching-Yu Chang

IPC: G03F7/004 ,  H01L21/033 ,  G03F7/00

CPC classification number: G03F7/004 ,  G03F7/0035 ,  H01L21/0332

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

公开(公告)号：US20230369048A1

公开(公告)日：2023-11-16

申请号：US18227231

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Lin WEI ,  Ming-Hui Weng ,  Chih-Cheng Liu ,  Yi-Chen Kuo ,  Yen-Yu Chen ,  Yahru Cheng ,  Jr-Hung Li ,  Ching-Yu Chang ,  Tze-Liang Lee ,  Chi-Ming Yang

IPC: H01L21/033 ,  H01L21/308 ,  G03F7/00 ,  G03F1/22

CPC classification number: H01L21/0332 ,  H01L21/3081 ,  G03F7/70033 ,  G03F1/22 ,  H01L21/0334

Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers. The multilayer photoresist structure is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying developer to the selectively exposed multilayer photoresist structure to form the pattern.

公开(公告)号：US20230282750A1

公开(公告)日：2023-09-07

申请号：US17841493

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Jr-Hung Li ,  Chi-Hao Chang ,  Hao-Yu Chang ,  Pei-Yu Chou

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: Methods of forming improved dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a transistor structure on a semiconductor substrate; a first dielectric layer on the transistor structure; a second dielectric layer on the first dielectric layer, the second dielectric layer having a nitrogen concentration greater than a nitrogen concentration of the first dielectric layer; a first conductive structure extending through the second dielectric layer and the first dielectric layer, the first conductive structure being electrically coupled to a first source/drain region of the transistor structure, a top surface of the first conductive structure being level with a top surface of the second dielectric layer; and a second conductive structure physically and electrically coupled to the first conductive structure, a bottom surface of the second conductive structure being a first distance below the top surface of the second dielectric layer.