公开(公告)号：US10658490B2

公开(公告)日：2020-05-19

申请号：US15663089

申请日：2017-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78 ,  H01L21/308 ,  H01L29/51

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes active gate stacks over the fin structure. The semiconductor device structure further includes a dummy gate stack over the fin structure. The dummy gate stack is between the active gate stacks. In addition, the semiconductor device structure includes spacer elements over sidewalls of the dummy gate stack and the active gate stacks. The semiconductor device structure also includes an isolation feature below the dummy gate stack, the active gate stacks and the spacer elements. The isolation feature extends into the fin structure from the bottom of the dummy gate stack such that the isolation feature is surrounded by the fin structure.

公开(公告)号：US20240405021A1

公开(公告)日：2024-12-05

申请号：US18468409

申请日：2023-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Chia-Hao Chang ,  Jia-Chuan You ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A device includes first nanostructures over a substrate; second nanostructures over the substrate, wherein the first nanostructures are laterally separated from the second nanostructures by an isolation structure between the first nanostructures and the second nanostructures; a first gate structure around each first nanostructure and around each second nanostructure, wherein the first gate structure extends over the isolation structure; third nanostructures over the substrate; and a second gate structure around each third nanostructure, wherein the second gate structure is separated from the first gate structure by a dielectric wall.

公开(公告)号：US20240387550A1

公开(公告)日：2024-11-21

申请号：US18788583

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Chih-Hao Wang ,  Shi Ning Ju ,  Jia-Chuan You ,  Kuo-Cheng Chiang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes providing a structure having two fins extending from a substrate; an isolation structure isolating bottom portions of the fins; source/drain (S/D) features over each of the fins; a dielectric fin oriented lengthwise parallel to the fins and disposed between the two fins and over the isolation structure; a dummy gate stack over the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers over sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack to result in a gate trench within the one or more dielectric layers, wherein the dielectric fin is exposed in the gate trench; trimming the dielectric fin to reduce a width of the dielectric fin; and after the trimming, forming a high-k metal gate in the gate trench.

公开(公告)号：US12100770B2

公开(公告)日：2024-09-24

申请号：US17379936

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi-Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Kuan-Lun Cheng ,  Guan-Lin Chen ,  Kuan-Ting Pan

IPC: H01L29/786 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66742

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.

公开(公告)号：US20240312987A1

公开(公告)日：2024-09-19

申请号：US18668911

申请日：2024-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Kuan-Ting Pan ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/762 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/76224 ,  H01L29/42392 ,  H01L29/78696

Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.

公开(公告)号：US20240250123A1

公开(公告)日：2024-07-25

申请号：US18591923

申请日：2024-02-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Huan-Chieh Su ,  Shi Ning Ju ,  Kuan-Ting Pan ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/0886 ,  H01L29/1033 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

公开(公告)号：US12014960B2

公开(公告)日：2024-06-18

申请号：US17234138

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Kuan-Ting Pan

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823462 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/7856 ,  H01L29/517

Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second polysilicon structures with first and second gate structures, respectively.

公开(公告)号：US20230402509A1

公开(公告)日：2023-12-14

申请号：US18150474

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Kuan-Ting Pan ,  Lung-Kun Chu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Jia-Ni Yu

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/78696 ,  H01L21/823807 ,  H01L21/76224 ,  H01L21/76831

Abstract: In an embodiment, a device includes: an isolation region on a substrate; first nanostructures above the isolation region; second nanostructures above the isolation region; a first gate spacer on the first nanostructures; a second gate spacer on the second nanostructures; a dielectric wall between the first gate spacer and the second gate spacer along a first direction in a top-down view, the dielectric wall disposed between the first nanostructures and the second nanostructures along a second direction in the top-down view, the first direction perpendicular to the second direction; and a gate structure around the first nanostructures and around the second nanostructures, a first portion of the gate structure filling a first area between the dielectric wall and the first nanostructures, a second portion of the gate structure filling a second area between the dielectric wall and the second nanostructures.

公开(公告)号：US11757021B2

公开(公告)日：2023-09-12

申请号：US16996781

申请日：2020-08-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Ruei Jhan ,  Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/308 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78696

Abstract: The present disclosure provide a method for using a hard mask layer on a top surface of fin structures to form a fin-top mask layer. The fin-top mask layer can function as an etch stop for subsequent processes. Using the fin-top hard mask layer allows a thinner conformal dielectric layer to be used to protect semiconductor fins during the subsequent process, such as during etching of sacrificial gate electrode layer. Using a thinner conformal dielectric layer can reduce the pitch of fins, particularly for input/output devices.

公开(公告)号：US11329165B2

公开(公告)日：2022-05-10

申请号：US16801423

申请日：2020-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Huan-Chieh Su ,  Kuan-Ting Pan ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device structure is provided, which includes a first fin structure over a semiconductor substrate. The first fin structure has multiple first semiconductor nanostructures suspended over the semiconductor substrate. The semiconductor device structure includes a second fin structure over the semiconductor substrate, and the second fin structure has multiple second semiconductor nanostructures suspended over the semiconductor substrate. The semiconductor device structure includes a dielectric fin between the first fin structure and the second fin structure. In addition, the semiconductor device structure includes a metal gate stack wrapping around the first fin structure, the second fin structure, and the dielectric fin. The semiconductor device structure includes a dielectric protection structure over the metal gate stack. The semiconductor device structure also includes an insulating structure penetrating through a bottom surface of the dielectric protection structure and extending into the metal gate stack to be aligned with the dielectric fin.