公开(公告)号：US11107907B2

公开(公告)日：2021-08-31

申请号：US16592422

申请日：2019-10-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Hao Chang ,  Li-Te Lin

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/311 ,  H01L21/3213

Abstract: A method for manufacturing a semiconductor device includes forming a dummy gate structure on a semiconductor fin; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor fin; forming a gate structure on the semiconductor fin and between the gate spacers, wherein the gate structure comprises a gate dielectric layer and a work function metal over the gate dielectric layer; performing a first plasma etching process by using a first reactant to etch back the gate structure performing a second plasma etching process by using a second reactant on the etched-back gate structure, wherein the first plasma etching process has a first removal rate of the gate dielectric layer, the second plasma etching process has a second removal rate of the gate dielectric layer, and the second removal rate is greater than the first removal rate.

公开(公告)号：US20210118674A1

公开(公告)日：2021-04-22

申请号：US17114070

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Ya-Wen Yeh ,  Wei-Liang Lin ,  Ya Chang ,  Yung-Sung Yen ,  Wei-Hao Wu ,  Li-Te Lin ,  Ru-Gun Liu ,  Kuei-Shun Chen

IPC: H01L21/027 ,  H01L21/033 ,  G03F7/09 ,  H01L21/311

Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate and forming a plurality of openings in the patterning layer. The substrate includes a plurality of features to receive a treatment process. The openings partially overlap with the features from a top view while a portion of the features remains covered by the patterning layer. Each of the openings is free of concave corners. The method further includes performing an opening expanding process to enlarge each of the openings and performing a treatment process to the features through the openings. After the opening expanding process, the openings fully overlap with the features from the top view.

公开(公告)号：US10957779B2

公开(公告)日：2021-03-23

申请号：US16158141

申请日：2018-10-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Jung-Hao Chang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/088 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01J37/00 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01L29/49 ,  H01L21/84 ,  H01L29/165 ,  H01L27/12

Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.

公开(公告)号：US10741671B2

公开(公告)日：2020-08-11

申请号：US16136339

申请日：2018-09-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Lo ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/033 ,  H01L21/027 ,  H01L29/423 ,  H01L21/308 ,  H01L21/768 ,  H01L29/78 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3213

Abstract: A method for manufacturing a semiconductor device, includes: forming a dummy gate structure on a semiconductor substrate; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; removing the dummy gate structure from the semiconductor substrate; forming a metal gate electrode on the semiconductor substrate and between the gate spacers; and performing a plasma etching process to the metal gate electrode, wherein the plasma etching process comprises performing in sequence a first non-zero bias etching step and a first zero bias etching step.

公开(公告)号：US20190067000A1

公开(公告)日：2019-02-28

申请号：US15689172

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Ya-Wen Yeh ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Wei-Hao Wu ,  Li-Te Lin ,  Ru-Gun Liu ,  Kuei-Shun Chen

IPC: H01L21/027 ,  G03F7/095 ,  G03F7/11 ,  H01L21/306 ,  G03F7/20 ,  H01L21/02

Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate, wherein the substrate includes a plurality of features to receive a treatment process; forming at least one opening in the patterning layer, wherein the plurality of features is partially exposed in the at least one opening; applying a directional etching to expand the at least one opening in a first direction, thereby forming at least one expanded opening; and performing the treatment process to the plurality of features through the at least one expanded opening.

公开(公告)号：US10157773B1

公开(公告)日：2018-12-18

申请号：US15823687

申请日：2017-11-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Shan Chen ,  Chan-Syun David Yang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/528 ,  H01L21/32 ,  H01L21/02

Abstract: A method of forming a semiconductor structure is provided. In this method, a semiconductor substrate is provided. A SoC layer is formed on the semiconductor substrate. A hard mask layer is formed over the SoC layer. The hard mask layer is patterned to expose a portion of the SoC layer. At least one opening is formed on the portion of the SoC layer using an ALE operation, thereby enabling the remaining portion of the SoC layer adjacent to the at least one opening to have a re-entrant angle included between a sidewall of the SoC layer and a bottom of the SoC layer.

公开(公告)号：US12261085B2

公开(公告)日：2025-03-25

申请号：US18359051

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Lun Chen ,  Li-Te Lin ,  Chao-Hsien Huang

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

公开(公告)号：US20240347345A1

公开(公告)日：2024-10-17

申请号：US18751423

申请日：2024-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Li-Te Lin ,  Pinyen Lin ,  Tze-Chung Lin

IPC: H01L21/311 ,  C23C16/452 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/311 ,  C23C16/452 ,  H01L21/31116 ,  H01L21/67063 ,  H01L21/67069 ,  H01L21/67098 ,  H01L21/67103 ,  H01L21/67115 ,  H01L21/6719 ,  H01L21/67225 ,  H01L21/67248 ,  H01L21/67748

Abstract: A semiconductor fabrication apparatus includes a processing chamber for etching, a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer, and a gas distribution plate integrated inside the processing chamber. The processing chamber includes a sidewall and a top surface. The semiconductor fabrication apparatus further includes a heating mechanism disposed on the sidewall of the processing chamber and is operable to perform a baking process to remove a by-product generated during the etching, and a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer, the reflective mirror being located on the top surface of the processing chamber. The gas distribution plate defines a portion of the top surface of the processing chamber. From a top view, a portion of the reflective mirror is disposed between the heating mechanism and the gas distribution plate.

公开(公告)号：US12087558B2

公开(公告)日：2024-09-10

申请号：US17402030

申请日：2021-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hao Chang ,  Po-Chin Chang ,  Pinyen Lin ,  Li-Te Lin

IPC: H01J37/32 ,  H01L21/263 ,  H01L21/687

CPC classification number: H01J37/32651 ,  H01J37/32422 ,  H01J37/32733 ,  H01L21/2633 ,  H01L21/68764 ,  H01J2237/334

Abstract: The present disclosure relates to a semiconductor device manufacturing system. The semiconductor device manufacturing system can include a chamber and an ion source in the chamber. The ion source can include an outlet. The ion source can be configured to generate a particle beam. The semiconductor device manufacturing system can further include a grid structure proximate to the outlet of the ion source and configured to manipulate the particle beam. A first portion of the grid structure can be electrically insulated from a second portion of the grid structure.

公开(公告)号：US20230369118A1

公开(公告)日：2023-11-16

申请号：US18359051

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Lun Chen ,  Li-Te Lin ,  Chao-Hsien Huang

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L21/823412 ,  H01L21/3065 ,  H01L21/31116 ,  H01L27/0886 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/0692 ,  H01L21/31144 ,  H01L29/66795 ,  H01L21/308 ,  H01L21/3086 ,  H01L29/1037 ,  H01L29/785 ,  H01L29/0657 ,  H01L29/1025 ,  H01L21/823431

Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.