公开(公告)号：US11682599B2

公开(公告)日：2023-06-20

申请号：US16199535

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L23/3114 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5389

Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure and adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.

公开(公告)号：US11430776B2

公开(公告)日：2022-08-30

申请号：US16902017

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

公开(公告)号：US11430739B2

公开(公告)日：2022-08-30

申请号：US16437297

申请日：2019-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Meng-Liang Lin ,  Shih-Yung Peng ,  Shih-Ting Hung

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

Abstract: Structures and formation methods of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes pressing a protective substrate against the carrier substrate at an elevated temperature to bond the protective substrate to the conductive structure. The method further includes forming a protective layer to surround the semiconductor die.

公开(公告)号：US20220199541A1

公开(公告)日：2022-06-23

申请号：US17690206

申请日：2022-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Yi-Wen Wu ,  Shin-Puu Jeng ,  Techi Wong

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

公开(公告)号：US11101214B2

公开(公告)日：2021-08-24

申请号：US16380502

申请日：2019-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Meng-Liang Lin ,  Yi-Wen Wu ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L23/495 ,  H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L25/07

Abstract: A package structure and method for forming the same are provided. The package structure includes a die structure formed over a first interconnect structure, and the die structure includes a first region and a second region. The package structure includes a dam structure formed on the first region of the die structure, and a second interconnect structure formed over the die structure and the dam structure. The package structure also includes a package layer formed between the first interconnect structure and the second interconnect structure, and the package layer is formed on the second region of the die structure to surround the dam structure.

公开(公告)号：US12199084B2

公开(公告)日：2025-01-14

申请号：US18525976

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Po-Yao Chuang ,  Shin-Puu Jeng ,  Meng-Wei Chou ,  Meng-Liang Lin

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

公开(公告)号：US20240105705A1

公开(公告)日：2024-03-28

申请号：US18525976

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Po-Yao Chuang ,  Shin-Puu Jeng ,  Meng-Wei Chou ,  Meng-Liang Lin

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L21/566 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/0401

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

公开(公告)号：US20240079356A1

公开(公告)日：2024-03-07

申请号：US18151623

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Chieh-Lung Lai ,  Meng-Liang Lin ,  Chun-Yueh Yang ,  Shin-Puu Jeng

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H10B80/00

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H10B80/00 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311

Abstract: An integrated circuit package includes an interposer, the interposer including: a first redistribution layer, a second redistribution layer over the first redistribution layer in a central region of the interposer, a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view, a third redistribution layer over the second redistribution layer and the dielectric layer, and a first direct via extending through the dielectric layer. A conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via.

公开(公告)号：US20230395581A1

公开(公告)日：2023-12-07

申请号：US17830187

申请日：2022-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Meng-Liang Lin ,  Shin-Puu Jeng

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L25/162 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/481 ,  H01L24/73

Abstract: A package is provided in accordance with some embodiments. The package includes a substrate including a first conductive via embedded in a first substrate core; a conductive pattern disposed on the first substrate core, wherein the conductive pattern includes a first conductive pad and a second conductive pad; a second substrate core disposed on the first substrate core and the conductive pattern; and a second conductive via disposed in the second substrate core and on the second conductive pad. The package also includes an encapsulant embedded in the second substrate core and in physical contact with the first conductive pad; a first die, including die connectors, embedded in the encapsulant and disposed on the first conductive pad; a redistribution structure disposed on the second conductive via, the die connectors and the encapsulant; and a second die disposed on the redistribution structure.

公开(公告)号：US20230361015A1

公开(公告)日：2023-11-09

申请号：US18351809

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L24/09 ,  H01L21/486 ,  H01L2924/3511 ,  H01L2224/02379

Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.