公开(公告)号：US09129823B2

公开(公告)日：2015-09-08

申请号：US13854507

申请日：2013-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L21/76 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: The embodiments described provide methods and semiconductor device areas for etching an active area region on a semiconductor body and epitaxially depositing a semiconductor layer overlying the active region. The methods enable the mitigation or elimination of problems encountered in subsequent manufacturing associated with STI divots.

Abstract translation: 所描述的实施例提供了用于蚀刻半导体主体上的有源区域并且外延沉积覆盖有源区域的半导体层的方法和半导体器件区域。 这些方法可以减轻或消除随后与STI科技相关的制造过程中遇到的问题。

公开(公告)号：US20220359489A1

公开(公告)日：2022-11-10

申请号：US17869968

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L25/18

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

公开(公告)号：US11075132B2

公开(公告)日：2021-07-27

申请号：US15939314

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu ,  Shih-Ting Hung ,  Yi-Jou Lin ,  Tzu-Jui Fang ,  Po-Yao Chuang

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/528 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

Abstract: An integrated fan-out package includes a first redistribution structure, a die, an encapsulant, a plurality of conductive structures, and a second redistribution structure. The first redistribution structure has a first surface and a second surface opposite to the first surface. The die is disposed over the first surface of the first redistribution structure and is electrically connected to the first redistribution structure. The encapsulant encapsulates the die. The conductive structures are disposed on the first surface of the first redistribution structure and penetrates the encapsulant. The conductive structures surround the die. The second redistribution structure is disposed on the encapsulant and is electrically connected to the first redistribution structure through the conductive structures. The second redistribution structure includes at least one conductive pattern layer that is in physical contact with the encapsulant.

公开(公告)号：US20210225776A1

公开(公告)日：2021-07-22

申请号：US16921907

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Shin-Puu Jeng ,  Shih-Ting Hung ,  Po-Yao Chuang

IPC: H01L23/552 ,  H01L23/538 ,  H01L25/16 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure. The global shielding structure is surrounding the first insulating encapsulant, the second insulating encapsulant, and covering sidewalls of the redistribution structure.

公开(公告)号：US20190096791A1

公开(公告)日：2019-03-28

申请号：US15876227

申请日：2018-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Dai-Jang Chen ,  Hsiang-Tai Lu ,  Hsien-Wen Liu ,  Chih-Hsien Lin ,  Shih-Ting Hung ,  Po-Yao Chuang

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L23/49822 ,  H01L21/56 ,  H01L22/14 ,  H01L22/32 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/81 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.

公开(公告)号：US09502533B2

公开(公告)日：2016-11-22

申请号：US14835958

申请日：2015-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L21/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract translation: 本公开的一些实施例涉及一种方法。 在该方法中，接收具有设置在半导体衬底中的有源区的半导体衬底。 形成浅沟槽隔离（STI）结构以横向围绕有源区域。 由STI结构限定的有源区的上表面凹入到STI结构的上表面的下方。 凹陷的上表面在STI结构的内侧壁之间连续延伸，并且使STI结构的内侧壁的上部露出。 在STI结构的内侧壁之间的有源区的凹面上外延生长半导体层。 在外延生长的半导体层上形成栅极电介质。 在栅极电介质上形成导电栅电极。

公开(公告)号：US12176337B2

公开(公告)日：2024-12-24

申请号：US17869968

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Techi Wong ,  Shih-Ting Hung ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

公开(公告)号：US11302650B2

公开(公告)日：2022-04-12

申请号：US16921907

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Shin-Puu Jeng ,  Shih-Ting Hung ,  Po-Yao Chuang

IPC: H01L23/552 ,  H01L23/538 ,  H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48

Abstract: A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure. The global shielding structure is surrounding the first insulating encapsulant, the second insulating encapsulant, and covering sidewalls of the redistribution structure.

公开(公告)号：US11114311B2

公开(公告)日：2021-09-07

申请号：US16242311

申请日：2019-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Shih-Ting Hung ,  Shin-Puu Jeng ,  Techi Wong

IPC: H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

Abstract: A method for forming a chip package structure is provided. The method includes forming a conductive structure over a substrate. The substrate includes a dielectric layer and a wiring layer in the dielectric layer, and the conductive structure is electrically connected to the wiring layer. The method includes forming a first molding layer over the substrate and surrounding the conductive structure. The method includes forming a redistribution structure over the first molding layer and the conductive structure. The method includes bonding a chip structure to the redistribution structure.

公开(公告)号：US20170062559A1

公开(公告)日：2017-03-02

申请号：US15349100

申请日：2016-11-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract translation: 本公开的一些实施例涉及一种方法。 在该方法中，接收具有设置在半导体衬底中的有源区的半导体衬底。 形成浅沟槽隔离（STI）结构以横向围绕有源区域。 由STI结构限定的有源区的上表面凹入到STI结构的上表面的下方。 凹陷的上表面在STI结构的内侧壁之间连续延伸，并且使STI结构的内侧壁的上部露出。 在STI结构的内侧壁之间的有源区的凹面上外延生长半导体层。 在外延生长的半导体层上形成栅极电介质。 在栅极电介质上形成导电栅电极。