公开(公告)号：US20170301709A1

公开(公告)日：2017-10-19

申请号：US15635673

申请日：2017-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Chih-Hui Huang ,  Shyh-Fann Ting ,  Shih Pei Chou ,  Sheng-Chan Li

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: The present disclosure relates to an integrated circuit, and an associated method of formation. In some embodiments, the integrated circuit comprises a deep trench grid disposed at a back side of a substrate. A passivation layer lines the deep trench grid within the substrate. The passivation layer includes a first high-k dielectric layer and a second high-k dielectric layer disposed over the first high-k dielectric layer. A first dielectric layer is disposed over the passivation layer, lining the deep trench grid and extending over an upper surface of the substrate. A second dielectric layer is disposed over the first dielectric layer and enclosing remaining spaces of the deep trench grid to form air-gaps at lower portions of the deep trench grid. The air-gaps are sealed by the first dielectric layer or the second dielectric layer below the upper surface of the substrate.

公开(公告)号：US09659981B2

公开(公告)日：2017-05-23

申请号：US13743979

申请日：2013-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shyh-Fann Ting ,  Chih-Yu Lai ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Ching-Chun Wang

IPC: H01L27/146

CPC classification number: H01L27/146 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14683

Abstract: A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these.

公开(公告)号：US09536810B1

公开(公告)日：2017-01-03

申请号：US14737979

申请日：2015-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Hsiao-Hui Tseng ,  Ming-Tsong Wang ,  Shyh-Fann Ting ,  Wei Chuang Wu

IPC: H01L23/482 ,  H01L27/146 ,  H01L23/485 ,  H01L23/48 ,  H01L23/528 ,  H01L31/05 ,  H01L31/0224

CPC classification number: H01L23/4824 ,  H01L21/76898 ,  H01L23/48 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14687 ,  H01L31/0224 ,  H01L31/05 ,  H01L31/0508

Abstract: A pad structure for a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. A semiconductor substrate is arranged over a back end of line (BEOL) metallization stack, and comprises a scribe line opening. A buffer layer lines the scribe line opening. A conductive pad comprises a base region and a protruding region. The base region is arranged over the buffer layer in the scribe line opening, and the protruding region protrudes from the base region into the BEOL metallization stack. A dielectric layer fills the scribe line opening over the conductive pad, and is substantially flush with an upper surface of the semiconductor substrate. Further, a method for manufacturing the pad structure, as well as the CMOS image sensor, are provided.

Abstract translation: 提供了一种用于互补金属氧化物半导体（CMOS）图像传感器的焊盘结构。 半导体衬底布置在线的后端（BEOL）金属化叠层上，并且包括划线开口。 缓冲层划线划线开口。 导电焊盘包括基极区域和突出区域。 基部区域布置在划线开口中的缓冲层上方，并且突出区域从基部区域突出到BEOL金属化堆叠中。 电介质层填充导电焊盘上的划线，并且与半导体衬底的上表面基本齐平。 此外，提供了一种用于制造焊盘结构的方法以及CMOS图像传感器。

公开(公告)号：US09425343B2

公开(公告)日：2016-08-23

申请号：US14016996

申请日：2013-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Lai ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Ching-Chun Wang

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L31/18 ,  H01L27/14614 ,  H01L27/14643

Abstract: Embodiments of mechanisms for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate and one photodetector formed in the semiconductor substrate. The image sensor device also includes one gate stack formed over the semiconductor substrate. The gate stack includes multiple polysilicon layers.

Abstract translation: 提供了用于形成图像传感器装置的机构的实施例。 图像传感器装置包括形成在半导体衬底中的半导体衬底和一个光电检测器。 图像传感器装置还包括形成在半导体衬底上的一个栅叠层。 栅堆叠包括多个多晶硅层。

公开(公告)号：US20230369380A1

公开(公告)日：2023-11-16

申请号：US17740544

申请日：2022-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Y.C. Chang ,  Yen-Ting Chiang ,  Shyh-Fann Ting ,  Jen-Cheng Liu

IPC: H01L27/146

CPC classification number: H01L27/14683 ,  H01L27/14643 ,  H01L27/14627 ,  H01L27/14621 ,  H01L27/14636

Abstract: The present disclosure describes an image sensor and a method for forming the image sensor. The image sensor includes an image sensing element disposed on a substrate, an extension pad disposed adjacent to the image sensing element, and a polysilicon pillar disposed on the extension pad. The image sensor further includes an insulating layer disposed over the image sensing element, the extension pad, and the polysilicon pillar.

公开(公告)号：US11444116B2

公开(公告)日：2022-09-13

申请号：US17135590

申请日：2020-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Wei Chia ,  Chun-Hao Chou ,  Kai-Chun Hsu ,  Kuo-Cheng Lee ,  Shyh-Fann Ting

IPC: H01L21/28 ,  H01L29/49 ,  H01L27/146

Abstract: A method includes depositing a gate dielectric layer over a substrate. A gate electrode layer, a protection oxide layer, and a hard mask are sequentially deposited over the gate dielectric layer. The gate electrode layer and the protection oxide layer are patterned by using the hard mask as an etching mask to form a gate structure over the gate dielectric layer. An etching process is performed to remove the hard mask and thin the protection oxide layer after forming the gate structure.

公开(公告)号：US11088196B2

公开(公告)日：2021-08-10

申请号：US16684871

申请日：2019-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Yimin Huang

IPC: H01L27/146

Abstract: The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.

公开(公告)号：US20210210534A1

公开(公告)日：2021-07-08

申请号：US16736134

申请日：2020-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Hsiao-Hui Tseng ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Wei Chuang Wu ,  Yen-Ting Chiang ,  Chia Ching Liao ,  Yen-Yu Chen

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

公开(公告)号：US10971534B2

公开(公告)日：2021-04-06

申请号：US16815409

申请日：2020-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Shyh-Fann Ting ,  Yen-Ting Chiang ,  Yeur-Luen Tu ,  Min-Ying Tsai

IPC: H01L27/146 ,  H04N5/365

Abstract: In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.

公开(公告)号：US20200212082A1

公开(公告)日：2020-07-02

申请号：US16815371

申请日：2020-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Shyh-Fann Ting ,  Yen-Ting Chiang ,  Yeur-Luen Tu ,  Min-Ying Tsai

IPC: H01L27/146

Abstract: In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.