公开(公告)号：US20210098283A1

公开(公告)日：2021-04-01

申请号：US16953949

申请日：2020-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shen-Nan LEE ,  Teng-Chun TSAI ,  Chen-Hao WU ,  Chu-An LEE ,  Chun-Hung LIAO ,  Tsung-Ling TSAI

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor structure is provided, including a conductive layer, a dielectric layer over the conductive layer, a ruthenium material in the dielectric layer and in contact with a portion of the conductive layer, and a ruthenium oxide material in the dielectric layer laterally between the ruthenium material and the dielectric layer.

公开(公告)号：US20200373160A1

公开(公告)日：2020-11-26

申请号：US16988635

申请日：2020-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei SU ,  Fu-Ting YEN ,  Teng-Chun TSAI

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3205 ,  H01L21/768 ,  H01L29/40

Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; removing a first portion of the dielectric layer to expose a first portion of the metal layer, while a second portion of the dielectric layer remains on the metal layer; selectively forming a first inhibitor on the second portion of the dielectric layer, while the metal layer is free of coverage by the first inhibitor; and selectively depositing a first hard mask on the exposed first portion of the metal layer, while the first inhibitor is free of coverage by the first hard mask.

公开(公告)号：US20200335388A1

公开(公告)日：2020-10-22

申请号：US16921015

申请日：2020-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun TSAI ,  Bing-Hung CHEN ,  Chien-Hsun WANG ,  Cheng-Tung LIN ,  Chih-Tang PENG ,  De-Fang CHEN ,  Huan-Just LIN ,  Li-Ting WANG ,  Yung-Cheng LU

IPC: H01L21/762 ,  H01L21/3105 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  B82Y10/00 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L29/41

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

公开(公告)号：US20200035677A1

公开(公告)日：2020-01-30

申请号：US16590248

申请日：2019-10-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shen-Nan LEE ,  Kuo-Yin LIN ,  Pin-Chuan SU ,  Teng-Chun TSAI

IPC: H01L27/088 ,  H01L29/66 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06

Abstract: A method includes following steps. A semiconductor substrate is etched to form semiconductor fins. A dielectric material is deposited into a trench between the semiconductor fins. The semiconductor fins are etched such that top ends of the semiconductor fins are lower than a top surface of the dielectric material. After etching the semiconductor fins, epitaxially growing epitaxial fins on the semiconductor fins, respectively. A chemical mechanical polish (CMP) process is performed on the epitaxial fins, followed by cleaning the epitaxial fins using a non-contact-type cleaning device. The dielectric material is then such that the top surface of the dielectric material is lower than top ends of the epitaxial fins. A gate structure is formed across the epitaxial fins.

公开(公告)号：US20190164762A1

公开(公告)日：2019-05-30

申请号：US16122235

申请日：2018-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei SU ,  Fu-Ting YEN ,  Ting-Ting CHEN ,  Teng-Chun TSAI

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/285 ,  H01L21/3105

Abstract: A method includes forming a gate stack and an interlayer dielectric (ILD) over a substrate, wherein the interlayer dielectric is adjacent to the gate stack; forming an inhibitor covering the interlayer dielectric such that the gate stack is exposed from the inhibitor; performing a deposition process to form a conductive layer over the gate stack until the conductive layer starts to form on the inhibitor, in which the deposition process has a deposition selectivity for the gate stack with respect to the inhibitor; and performing an etching process to remove a portion of the conductive layer over the inhibitor.

公开(公告)号：US20240332073A1

公开(公告)日：2024-10-03

申请号：US18738390

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang LIN ,  Wei-Hao WU ,  Teng-Chun TSAI

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L21/76835 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53295 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4232

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.

公开(公告)号：US20230146366A1

公开(公告)日：2023-05-11

申请号：US18152952

申请日：2023-01-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei SU ,  Fu-Ting YEN ,  Ting-Ting CHEN ,  Teng-Chun TSAI

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3205

CPC classification number: H01L21/28088 ,  H01L21/28079 ,  H01L21/32135 ,  H01L21/02118 ,  H01L29/6656 ,  H01L21/31116 ,  H01L21/02282 ,  H01L21/0206 ,  H01L21/28556 ,  H01L21/31058 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/32051 ,  H01L29/66795 ,  H01L21/32

Abstract: A device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, source/drain structures over the substrate and on opposite sides of the gate structure, and a self-assemble monolayer (SAM) in contact with an inner sidewall of one of the gate spacer and in contact with a top surface of the gate structure.

公开(公告)号：US20210384322A1

公开(公告)日：2021-12-09

申请号：US17408985

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang LIN ,  Teng-Chun TSAI ,  Huang-Lin CHAO ,  Akira MINEJI

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/49 ,  H01L21/311 ,  H01L21/321 ,  H01L29/78

Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

公开(公告)号：US20200091007A1

公开(公告)日：2020-03-19

申请号：US16277326

申请日：2019-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chu-An LEE ,  Chen-Hao WU ,  Peng-Chung JANGJIAN ,  Chun-Wen HSIAO ,  Teng-Chun TSAI ,  Huang-Lin CHAO

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate, an isolation feature between and adjacent to the first fin and the second fin, and a fin isolation structure between the first fin and the second fin. The fin isolation structure includes a first insulating layer partially embedded in the isolation feature, a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer, a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer, and a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.

公开(公告)号：US20190237364A1

公开(公告)日：2019-08-01

申请号：US16378162

申请日：2019-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yee-Chia YEO ,  Teng-Chun TSAI ,  Yasutoshi OKUNO

IPC: H01L21/768 ,  H01L21/308 ,  H01L23/522 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L21/76879 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3088 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1063

Abstract: The present disclosure describes a method of forming a replacement contact. For example, the replacement contact can include a metal with one or more first sidewall surfaces and a top surface. A first dielectric can be formed to abut the one or more first sidewall surfaces of the metal. A second dielectric can be formed over the first dielectric and the top surface of the metal. An opening in the second dielectric can be formed. A metal oxide structure can be selectively grown on the top surface of the metal, where the metal oxide structure has one or more second sidewall surfaces. One or more spacers can be formed to abut the one or more second sidewall surfaces of the metal oxide structure. Further, the metal oxide structure can be removed.