公开(公告)号：US20190378928A1

公开(公告)日：2019-12-12

申请号：US16504670

申请日：2019-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ying-Lang Wang

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3215

Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.

公开(公告)号：US10347762B1

公开(公告)日：2019-07-09

申请号：US15991570

申请日：2018-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ying-Lang Wang

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/165 ,  H01L21/3215

Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.

公开(公告)号：US10058974B1

公开(公告)日：2018-08-28

申请号：US15475269

申请日：2017-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hung Chen ,  Kei-Wei Chen ,  Ying-Lang Wang

IPC: H01L21/302 ,  B24B37/013 ,  B24B37/04 ,  B24B49/16 ,  H01L21/306 ,  H01L21/321

CPC classification number: B24B37/013 ,  B24B37/042 ,  B24B37/107 ,  B24B49/16

Abstract: A method for performing a CMP process is provided. The method includes performing the CMP process. The method further includes during the CMP process detecting a motion of a carrier head about a rotation axis beside a polishing pad. The method also includes producing a control signal corresponding to a detected result of the motion. In addition, the method includes prohibiting the rotation of the carrier head about a rotation axis by a driving motor which is controlled by the control signal. And, the method includes selecting a point of time at which the CMP process is terminated after the control signal is substantially the same as a threshold value.

公开(公告)号：US20170250281A1

公开(公告)日：2017-08-31

申请号：US15054089

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Ziwei Fang ,  Shiu-Ko JangJian ,  Kei-Wei Chen ,  Huai-Tei Yang ,  Ying-Lang Wang

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/161 ,  H01L27/12 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/1211 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, first spacers, second spacers and source and drain regions is described. The substrate has fins and insulators disposed between the fins. The at least one gate structure is disposed over the fins and disposed on the insulators. The first spacers are disposed on opposite sidewalls of the at least one gate structure. The source and drain regions are disposed on two opposite sides of the at least one gate structure and beside the first spacers. The second spacers are disposed on the two opposite sides of the at least one gate structure and beside the first spacers. The source and drain regions are sandwiched between the opposite second spacers.

公开(公告)号：US12068195B2

公开(公告)日：2024-08-20

申请号：US18330466

申请日：2023-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/76825 ,  H01L23/5226 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/00 ,  H01L2924/0002

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

公开(公告)号：US11955553B2

公开(公告)日：2024-04-09

申请号：US18174045

申请日：2023-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Wen-Yen Chen ,  Ying-Lang Wang ,  Liang-Yin Chen ,  Li-Ting Wang ,  Huicheng Chang

IPC: H01L21/24 ,  H01L21/02 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/02694 ,  H01L21/324 ,  H01L21/76829 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6681

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

公开(公告)号：US20220122884A1

公开(公告)日：2022-04-21

申请号：US17646024

申请日：2021-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

公开(公告)号：US10854713B2

公开(公告)日：2020-12-01

申请号：US15865072

申请日：2018-01-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming Lin ,  Shiu-Ko Jangjian ,  Chun-Che Lin ,  Ying-Lang Wang ,  Wei-Ken Lin ,  Chuan-Pu Liu

IPC: H01L21/3105 ,  H01L21/314 ,  H01L21/324 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/12 ,  H01L21/84

Abstract: A method includes forming a flowable dielectric layer in a trench of a substrate; curing the flowable dielectric layer; and annealing the cured flowable dielectric layer to form an insulation structure and a liner layer. The insulation structure is formed in the trench, the liner layer is formed between the insulation structure and the substrate, and the liner layer includes nitrogen.

公开(公告)号：US10573749B2

公开(公告)日：2020-02-25

申请号：US15054089

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Ziwei Fang ,  Shiu-Ko JangJian ,  Kei-Wei Chen ,  Huai-Tei Yang ,  Ying-Lang Wang

IPC: H01L27/01 ,  H01L29/78 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, first spacers, second spacers and source and drain regions is described. The substrate has fins and insulators disposed between the fins. The at least one gate structure is disposed over the fins and disposed on the insulators. The first spacers are disposed on opposite sidewalls of the at least one gate structure. The source and drain regions are disposed on two opposite sides of the at least one gate structure and beside the first spacers. The second spacers are disposed on the two opposite sides of the at least one gate structure and beside the first spacers. The source and drain regions are sandwiched between the opposite second spacers.

公开(公告)号：US09812569B2

公开(公告)日：2017-11-07

申请号：US14224961

申请日：2014-03-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Chih Chen ,  Ying-Lang Wang ,  Chih-Mu Huang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.