公开(公告)号：US09721826B1

公开(公告)日：2017-08-01

申请号：US15007041

申请日：2016-01-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Yu Ma ,  Yii-Chi Lin ,  Zheng-Yang Pan ,  Chia-Chiung Lo

IPC: B23P19/04 ,  H01L21/687 ,  H01L21/67 ,  H01L21/66 ,  H01L21/324

CPC classification number: H01L21/68785 ,  H01L21/324 ,  H01L21/67115 ,  H01L21/67248 ,  H01L21/68757 ,  H01L21/68792 ,  H01L22/20

Abstract: A wafer supporting structure in semiconductor manufacturing, and a device and a method for manufacturing semiconductor are provided. In accordance with some embodiments of the instant disclosure, a wafer supporting structure in semiconductor manufacturing includes a transparent ring and at least two arms. The arms are connected to the transparent ring.

公开(公告)号：US11677015B2

公开(公告)日：2023-06-13

申请号：US17109895

申请日：2020-12-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ya-Wen Chiu ,  Yi Che Chan ,  Lun-Kuang Tan ,  Zheng-Yang Pan ,  Cheng-Po Chau ,  Pin-Ju Liang ,  Hung-Yao Chen ,  De-Wei Yu ,  Yi-Cheng Li

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/161 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L29/66818 ,  H01L21/0262 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/6681 ,  H01L29/7851

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

公开(公告)号：US10026840B2

公开(公告)日：2018-07-17

申请号：US15292428

申请日：2016-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Zheng-Yang Pan ,  Chun-Chieh Wang ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/267 ,  H01L29/36 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234

Abstract: Structures of a semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, and a first recess and a second recess in the substrate and at opposite sides of the gate structure. The semiconductor device also includes two source/drain structures over the first recess and the second recess respectively. At least one of the source/drain structures includes a first doped region partially filling in the first recess, a second doped region over the first doped region, and a third doped region over the second doped region. The second doped region contains more dopants than the first doped region or the third doped region.

公开(公告)号：US20240379450A1

公开(公告)日：2024-11-14

申请号：US18780110

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi Chen Ho ,  Yiting Chang ,  Chi-Hsun Lin ,  Zheng-Yang Pan

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/762 ,  H01L27/088

Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.

公开(公告)号：US20240363442A1

公开(公告)日：2024-10-31

申请号：US18770052

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Chun Chieh Wang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823857 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/823418 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

公开(公告)号：US12107015B2

公开(公告)日：2024-10-01

申请号：US17232381

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Chun Chieh Wang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823857 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/823418 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

公开(公告)号：US20230008893A1

公开(公告)日：2023-01-12

申请号：US17483043

申请日：2021-09-23

Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

Inventor： Yi Chen Ho ,  Yiting Chang ,  Chi-Hsun Lin ,  Zheng-Yang Pan

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762

Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.

公开(公告)号：US20220262681A1

公开(公告)日：2022-08-18

申请号：US17734521

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Ma ,  Zheng-Yang Pan ,  Shahaji B. More ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/485 ,  H01L29/08

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

公开(公告)号：US11233123B2

公开(公告)日：2022-01-25

申请号：US16741607

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Huai-Tei Yang ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Chun-Chieh Wang ,  Cheng-Han Lee

IPC: H01L29/10 ,  H01L21/8238 ,  H01L21/74 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.

公开(公告)号：US20190157154A1

公开(公告)日：2019-05-23

申请号：US15819129

申请日：2017-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Wang ,  Huai-Tei Yang ,  Zheng-Yang Pan ,  Shahaji B. More ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06

Abstract: The present disclosure describes an exemplary fabrication method of a p-type fully strained channel that can suppress the formation of {111} facets during a silicon germanium epitaxial growth. The exemplary method includes the formation of silicon epitaxial layer on a top, carbon-doped region of an n-type region. A recess is formed in the silicon epitaxial layer via etching, where the recess exposes the top, carbon-doped region of the n-type region. A silicon seed layer is grown in the recess, and a silicon germanium layer is subsequently epitaxially grown on the silicon seed layer to fill the recess. The silicon seed layer can suppress the formation of growth defects such as, for example, {111} facets, during the silicon germanium epitaxial layer growth.