公开(公告)号：US11984375B2

公开(公告)日：2024-05-14

申请号：US18302589

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Ling Tsai ,  Jiun Yi Wu ,  Chien-Hsun Lee ,  Chung-Shi Liu

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/3121 ,  H01L23/49827 ,  H01L23/5384

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

公开(公告)号：US20230326850A1

公开(公告)日：2023-10-12

申请号：US18334843

申请日：2023-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chien-Hsun Chen

IPC: H01L23/522 ,  H01L25/16 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L25/16 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/97 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/02373

Abstract: A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.

公开(公告)号：US20230091737A1

公开(公告)日：2023-03-23

申请号：US17994841

申请日：2022-11-28

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/522 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US20210296243A1

公开(公告)日：2021-09-23

申请号：US16824722

申请日：2020-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun-Yi Wu ,  Chien-Hsun Lee ,  Shou-Yi Wang ,  Chien-Hsun Chen

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L21/52 ,  H01L23/00

Abstract: A package has a first semiconductor die, a second semiconductor die, a redistribution structure and a metallic bolstering pattern. The second semiconductor die is disposed beside the first semiconductor die and spaced apart from the first semiconductor die with a distance. The redistribution structure is disposed over the first semiconductor die and the second semiconductor die and is electrically connected with the first and second semiconductor dies. The metallic bolstering pattern is disposed between the redistribution structure and the first and second semiconductor dies. The metallic bolstering pattern is disposed on the redistribution structure and located over the first and second semiconductor dies, and the metallic bolstering pattern extends across the distance between the first and second semiconductor dies and extends beyond borders of the first and second semiconductor dies.

公开(公告)号：US20210057346A1

公开(公告)日：2021-02-25

申请号：US16547567

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Wei-Ting Chen ,  Chien-Hsun Chen ,  Shih-Ya Huang

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

Abstract: A semiconductor package includes dies, a redistribution structure, a conductive structure and connectors. The conductive plate is electrically connected to contact pads of at least two dies and is disposed on redistribution structure. The conductive structure includes a conductive plate and a solder cover, and the conductive structure extend over the at least two dies. The connectors are disposed on the redistribution structure, and at least one connector includes a conductive pillar. The conductive plate is at same level height as conductive pillar. The vertical projection of the conductive plate falls on spans of the at least two dies.

公开(公告)号：US20240258187A1

公开(公告)日：2024-08-01

申请号：US18631966

申请日：2024-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Ling Tsai ,  Jiun Yi Wu ,  Chien-Hsun Lee ,  Chung-Shi Liu

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/3121 ,  H01L23/49827 ,  H01L23/5384

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

公开(公告)号：US11715686B2

公开(公告)日：2023-08-01

申请号：US17222225

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chien-Hsun Chen

IPC: H01L23/522 ,  H01L25/16 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401

Abstract: A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.

公开(公告)号：US20230223357A1

公开(公告)日：2023-07-13

申请号：US17752272

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Che Chiang ,  Chien-Hsun Chen ,  Tuan-Yu Hung ,  Hsin-Yu Pan ,  Wei-Kang Hsieh ,  Tsung-Hsien Chiang ,  Chao-Hsien Huang ,  Tzu-Sung Huang ,  Ming Hung Tseng ,  Wei-Chih Chen ,  Ban-Li Wu ,  Hao-Yi Tsai ,  Yu-Hsiang Hu ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L25/105 ,  H01L24/20 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L24/19 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2224/214 ,  H01L2221/68359 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.

公开(公告)号：US11515173B2

公开(公告)日：2022-11-29

申请号：US16869066

申请日：2020-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/31 ,  H01L23/48

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US20220093498A1

公开(公告)日：2022-03-24

申请号：US17457728

申请日：2021-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/66 ,  H05K3/40

Abstract: A method includes forming a first redistribution line, forming a polymer layer including a first portion encircling the first redistribution line and a second portion overlapping the first redistribution line, forming a pair of differential transmission lines over and contacting the polymer layer, and molding the pair of differential transmission lines in a molding compound. The molding compound includes a first portion encircling the pair of differential transmission lines, and a second portion overlapping the pair of differential transmission lines. An electrical connector is formed over and electrically coupling to the pair of differential transmission lines.