公开(公告)号：US11341085B2

公开(公告)日：2022-05-24

申请号：US16920901

申请日：2020-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

公开(公告)号：US11016842B2

公开(公告)日：2021-05-25

申请号：US16122575

申请日：2018-09-05

Applicant: Texas Instruments Incorporated

Inventor： Yuming Zhu ,  Manish Goel ,  Sai Zhang

IPC: G11C29/44 ,  G11C29/52 ,  G11C29/04 ,  G11C29/42 ,  G11C29/20 ,  G06F11/10 ,  G06F11/30 ,  G11C16/26 ,  G11C16/30 ,  G11C11/22 ,  G11C29/02

Abstract: In described examples, data are stored in a destructive read non-volatile memory (DRNVM). The DRNVM includes an array of DRNVM cells organized as rows of data. The rows of data are subdivided into columns of code word symbols. Each column of code word symbols is encoded to store an error correction code symbol for each column of code word symbols.

公开(公告)号：US20210109579A1

公开(公告)日：2021-04-15

申请号：US17130076

申请日：2020-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Clive Bittlestone ,  Joyce Kwong ,  Manish Goel

IPC: G06F1/26 ,  H04L9/32 ,  G06F21/73

Abstract: Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes decreasing a supply voltage of a memory array to a first voltage level, the first voltage level being below a normal operating voltage associated with the memory array, reading a first value of a bit cell after the supply voltage has been at the first voltage level, and determining a function based on the first value of the bit cell and a second value, the second value stored in the bit cell when the memory array is operating at a voltage level above the first voltage level, the function to represent an identification of a circuit including the memory array.

公开(公告)号：US10241791B2

公开(公告)日：2019-03-26

申请号：US15925957

申请日：2018-03-20

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F9/30 ,  G06F13/16 ,  G06F13/40 ,  G06F9/38

Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor configured to execute instruction words received on the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers are coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

公开(公告)号：US10152613B2

公开(公告)日：2018-12-11

申请号：US15898935

申请日：2018-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joyce Kwong ,  Clive Bittlestone ,  Manish Goel

IPC: G06F21/73 ,  G11C11/419 ,  G11C29/50 ,  G09C1/00 ,  H04L9/32 ,  G11C29/44

Abstract: Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes after applying a voltage to a memory array: determining a first duration between the applying of the voltage and a first output of a first bit cell, the first output corresponding to a first value stored in the first bit cell, and determining a second duration between the applying of the voltage and a second output of a second bit cell, the second output corresponding to a second value stored in the second bit cell. The example method further includes determining a function based on a comparison of the first duration and the second duration, the function to establish an identification of a circuit that includes the memory array.

公开(公告)号：US20180012642A1

公开(公告)日：2018-01-11

申请号：US15710971

申请日：2017-09-21

Applicant: Texas Instruments Incorporated

Inventor： Jose A. Rodriguez-Latorre ,  Hugh P. McAdams ,  Manish Goel

IPC: G11C11/22 ,  G06F11/10 ,  H03M13/29 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C11/2275 ,  G06F11/1008 ,  G06F11/1068 ,  G11C11/221 ,  G11C11/2273 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/2945

Abstract: Disclosed embodiments include a memory device having a memory array that includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line and a sense amplifier that includes first and second transistors arranged in a cross-coupled configuration with third and fourth transistors, the first and second transistors being of a first conductivity type and the third and fourth transistors being of a second conductivity type, a first inverter having an input coupled to a first common drain terminal of the first and third transistors and an output coupled to the first bit line, and a second inverter having an input coupled to a second common drain terminal of the second and fourth transistors and an output coupled to the second bit line.

公开(公告)号：US09817791B2

公开(公告)日：2017-11-14

申请号：US14678939

申请日：2015-04-04

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland, GMBH

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F15/80 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/325 ,  G06F9/3822 ,  G06F9/3853 ,  G06F9/3877

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

公开(公告)号：US09715943B2

公开(公告)日：2017-07-25

申请号：US14824935

申请日：2015-08-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yuming Zhu ,  Manish Goel ,  Clive Bittlestone ,  Yunchen Qiu ,  Sai Zhang

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G11C16/34 ,  G11C7/10

CPC classification number: G11C29/38 ,  G11C7/1006 ,  G11C7/24 ,  G11C16/22 ,  G11C16/349 ,  G11C17/16 ,  G11C17/18 ,  G11C29/36 ,  G11C2207/2263

Abstract: Data words to be written to a memory location are delta encoded in multi-write avoidance (“MWA”) code words. MWA code words result in no re-writing of single-bit storage cells containing logical “0's” to a “0” state and no re-writing of logical “1's” to cells that have already been written once to a logical “1.” Potential MWA code words stored in a look-up table (“LUT”) are indexed by a difference word DELTA_D. DELTA_D represents a bitwise difference (“delta”) between a data word currently stored at the memory location and a new data word (“NEW_D”) to be stored at the memory location. Validation and selection logic chooses an MWA code word representing NEW_D to be written if the MWA code word does not violate the principle of multi-write avoidance. Some embodiments generate the MWA code words using a pattern generator rather than indexing the MWA code words from a LUT.

公开(公告)号：US09584542B2

公开(公告)日：2017-02-28

申请号：US14614038

申请日：2015-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hun-Seok Kim ,  Anand Ganesh Dabak ,  Jing-Fei Ren ,  Manish Goel

IPC: H04L29/06 ,  H04L29/08 ,  H04L9/32 ,  H04W12/12

CPC classification number: H04L63/1466 ,  H04K1/003 ,  H04K3/25 ,  H04K3/46 ,  H04K3/65 ,  H04K3/827 ,  H04K3/86 ,  H04K2203/22 ,  H04L9/3271 ,  H04L67/12 ,  H04L2209/805 ,  H04W12/12

Abstract: An apparatus for preventing a relay attack that includes a microcontroller, a receiver, and a transmitter. The receiver is configured to receive a challenge message from a verifier. The challenge message has a challenge message frequency at a first challenge message frequency during a first time slot. The transmitter is configured to transmit a response message to the verifier. The response message has a response message frequency at a first response message frequency during the first time slot. The first response message frequency is different than the first challenge message frequency. The challenge message frequency is at a second challenge message frequency and the response message frequency is at a second response message frequency during a second time slit. The second challenge message frequency is different than the second response message frequency.

Abstract translation: 一种用于防止包括微控制器，接收器和发射器的中继攻击的装置。 接收器被配置为从验证器接收挑战消息。 挑战消息在第一时隙期间在第一挑战消息频率处具有挑战消息频率。 发送器被配置为向验证者发送响应消息。 响应消息在第一时隙期间具有在第一响应消息频率处的响应消息频率。 第一响应消息频率与第一挑战消息频率不同。 挑战消息频率处于第二挑战消息频率，并且响应消息频率在第二时间缝隙期间处于第二响应消息频率。 第二挑战消息频率与第二响应消息频率不同。

公开(公告)号：US20160291974A1

公开(公告)日：2016-10-06

申请号：US14678944

申请日：2015-04-04

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland, GMBH

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F9/30 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F9/3013 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/3877 ,  G06F9/3889 ,  G06F13/1678 ,  G06F13/4018 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus for a low energy accelerator processor architecture. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory ; a low energy accelerator processor configured to execute instruction words coupled to the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to retrieved instruction words; and a non-orthogonal data register file comprising a set of data registers coupled to the plurality of execution units, the registers coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

Abstract translation: 低能量加速器处理器架构的设备。 示例性布置是包括具有数据宽度N的系统总线的集成电路，其中N是正整数; 耦合到所述系统总线并被配置为执行从存储器检索的指令的中央处理器单元; 低能量加速器处理器，被配置为执行与所述系统总线耦合的指令字，并具有多个执行单元，所述多个执行单元包括加载存储单元，负载系数单元，乘法单元和蝶形/加法器ALU单元，每个执行单元 被配置为响应于检索到的指令字执行操作; 以及非正交数据寄存器文件，其包括耦合到所述多个执行单元的一组数据寄存器，所述寄存器耦合到所述多个执行单元中的所选择的执行单元。 公开了附加的方法和装置。