公开(公告)号：US20230268826A1

公开(公告)日：2023-08-24

申请号：US17677072

申请日：2022-02-22

Applicant: Texas Instruments Incorporated

Inventor： Yi Yan ,  Vivek Arora

IPC: H02M3/00 ,  H02M3/335 ,  H05K7/20 ,  H01F27/30 ,  H01F41/02

CPC classification number: H02M3/003 ,  H02M3/33523 ,  H05K7/2089 ,  H01F27/30 ,  H01F41/0246

Abstract: An isolated power converter package includes a leadframe including a first and second die pad, first and second supports connected to first leads, second leads. A first semiconductor die is on the first die pad and a second semiconductor die is on the second die pad. The molded transformer includes a top and bottom side magnetic sheet each having a magnetic mold material including magnetic particles in a second dielectric material on respective sides of a laminate substrate including a dielectric material and a first coil and a second coil that each include a coil contact. Edges of the laminate substrate are on the supports. Bond wires are between the first die bond pads and the second leads, between the second die bond pads and the second leads, between the first die bond pads and coil contacts, and between the second die bond pads and the coil contacts.

公开(公告)号：US20230245942A1

公开(公告)日：2023-08-03

申请号：US17589761

申请日：2022-01-31

Applicant: Texas Instruments Incorporated

Inventor： Kwang-Soo Kim ,  Woochan Kim ,  Vivek Arora ,  Ken Pham

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/34 ,  H01L23/49555 ,  H01L24/06 ,  H01L23/3107 ,  H01L21/4803 ,  H01L24/48 ,  H01L2224/06135 ,  H01L2224/48175

Abstract: A described example includes: a heat slug having a board side surface and an opposite top side surface; a package substrate mounted to the heat slug, the package substrate including overhanging leads extending over the board side surface of the heat slug, the package substrate having downset portions including a downset rail that runs along one side of a die mount area; at least one semiconductor device having a backside surface mounted to the board side surface of the heat slug; electrical connections coupling bond pads of the semiconductor device to the overhanging leads of the package substrate and to the downset rail; and mold compound covering the at least one semiconductor device, the electrical connections, a portion of the leads and the board side surface of the heat slug, the top side surface at least partially exposed from the mold compound.

公开(公告)号：US20230059142A1

公开(公告)日：2023-02-23

申请号：US17404765

申请日：2021-08-17

Applicant: Texas Instruments Incorporated

Inventor： Vivek Arora ,  Woochan Kim ,  Anindya Poddar

IPC: H01L23/433 ,  H01L23/31 ,  H01L23/00 ,  H01L23/495

Abstract: In a described example, an apparatus includes: a package substrate having a die mount surface; semiconductor die flip chip mounted to the package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the active surface of the semiconductor die and connected to the package substrate by solder joints; a thermal interposer comprising a thermally conductive material positioned over and in thermal contact with a backside surface of the semiconductor die; and mold compound covering a portion of the package substrate, a portion of the thermal interposer, the semiconductor die, and the post connects, the thermal interposer having a surface exposed from the mold compound.

公开(公告)号：US20200235067A1

公开(公告)日：2020-07-23

申请号：US16253680

申请日：2019-01-22

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Dibyajat Mishra ,  Kurt Sincerbox ,  Vivek Arora

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/07 ,  H01L25/00

Abstract: A packaged electronic device includes a multilayer substrate, including a first side, a first layer having a first plurality of conductive structures along the first side, and a second layer having a second plurality of conductive structures, a semiconductor die soldered to a first set of the conductive structures, a conductive clip directly connected to one of the conductive structures of the first layer and to a second side of the semiconductor die, and a package structure that encloses the semiconductor die and a portion of the conductive clip.

公开(公告)号：US20240194546A1

公开(公告)日：2024-06-13

申请号：US18078923

申请日：2022-12-10

Applicant: Texas Instruments Incorporated

Inventor： Kwang-Soo Kim ,  Vivek Arora ,  Ken Pham

IPC: H01L23/08 ,  H01L23/00 ,  H01L23/492 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L23/08 ,  H01L23/492 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/32221 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247

Abstract: An electronic device includes a multilevel ceramic body, first, second, and third plates, and first and second semiconductor dies, with the multilevel ceramic body having opposite first and second sides, a first and second openings in the first side, a third opening in the second side, and a ceramic separator structure defining first and second interior portions between the first and second openings. The first plate is attached to the first side and covers the first opening, the second plate is attached to the first side and covers the second opening, the third plate is attached to the second side and covers the third opening, the first semiconductor die is in the first interior portion, and the second semiconductor die is in the second interior portion of the ceramic body.

公开(公告)号：US20240038619A1

公开(公告)日：2024-02-01

申请号：US17876621

申请日：2022-07-29

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Kwang-Soo Kim ,  Vivek Arora

IPC: H01L23/367 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/373

CPC classification number: H01L23/3675 ,  H01L24/83 ,  H01L24/32 ,  H01L21/4882 ,  H01L23/5389 ,  H01L23/3735 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/3512 ,  H01L2924/1711 ,  H01L2924/172 ,  H01L2924/173 ,  H01L2924/176 ,  H01L2924/1033 ,  H01L2224/83862 ,  H01L2224/3201 ,  H01L2224/83203

Abstract: An electronic device includes an embedded die frame having a cavity and a routing structure, a semiconductor die in the cavity with a gallium nitride layer on the routing structure, and a heat spreader having a thermally conductive insulator layer and a metal plate, the thermally conductive insulator layer having a first side that faces the embedded die frame and an opposite second side that faces away from the embedded die frame, with a portion of the first side of the thermally conductive insulator layer extending over a side of a silicon substrate of the semiconductor die, and the metal plate on the second side of the thermally conductive insulator layer.

公开(公告)号：US20240038429A1

公开(公告)日：2024-02-01

申请号：US17873785

申请日：2022-07-26

Applicant: Texas Instruments Incorporated

Inventor： Yi Yan ,  Vivek Arora

IPC: H01F17/00 ,  H01F27/28 ,  H01L23/48 ,  H01L23/64

CPC classification number: H01F17/0033 ,  H01F17/0013 ,  H01F27/2804 ,  H01L23/481 ,  H01L23/645 ,  H01F2027/2809 ,  H01F2017/0086 ,  H01F2017/0073 ,  H01F2017/002

Abstract: An electronic device with an integrated transformer including a first substrate having a first patterned conductive feature with multiple turns that form a first winding, and a first molded magnetic material that encloses a portion of the first patterned conductive feature, and an adhesive layer on a side of the first substrate. The transformer also includes a second substrate having a second patterned conductive feature with multiple turns that form a second winding, and a second molded magnetic material that encloses a portion of the second patterned conductive feature, the second substrate extending on the adhesive layer to magnetically couple the first and second windings. The electronic device includes a package structure that encloses the first and second substrates.

公开(公告)号：US11329025B2

公开(公告)日：2022-05-10

申请号：US16828298

申请日：2020-03-24

Applicant: Texas Instruments Incorporated

Inventor： Vivek Arora ,  Woochan Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/492 ,  H01L23/495 ,  H01L21/56 ,  H01F27/40 ,  H01F27/06 ,  H01L25/00

Abstract: A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.

公开(公告)号：US20210305207A1

公开(公告)日：2021-09-30

申请号：US16828298

申请日：2020-03-24

Applicant: Texas Instruments Incorporated

Inventor： Vivek Arora ,  Woochan Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/492 ,  H01L23/495 ,  H01L25/00 ,  H01L21/56 ,  H01F27/40 ,  H01F27/06

Abstract: A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.

公开(公告)号：US11075147B2

公开(公告)日：2021-07-27

申请号：US16504816

申请日：2019-07-08

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Arora ,  Ken Pham

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/64 ,  H01L21/48

Abstract: A stacked die semiconductor package includes a leadframe including a die pad and lead terminals on at least two sides of the die pad, a top die having circuitry coupled to bond pads, and bottom die having a back side that is attached by die attach material to the die pad and a top side having at least one redistribution layer (RDL) over and coupled to a top metal level including connections to input/output (IO) nodes on the top metal level. The RDL provides a metal pattern including wirebond pads that match locations of the bond pads of the top die. The bond pads on the top die are flip-chip attached to the wirebond pads of the bottom die, and the bond wires are positioned between the wirebond pads and the lead terminals.