公开(公告)号：US06897502B2

公开(公告)日：2005-05-24

申请号：US10620698

申请日：2003-07-17

申请人： Shinichi Watanabe ,  Toyota Morimoto ,  Tohru Ozaki ,  Haruhiko Koyama

发明人： Shinichi Watanabe ,  Toyota Morimoto ,  Tohru Ozaki ,  Haruhiko Koyama

IPC分类号： H01L27/105 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A first impurity diffusion area is formed in the semiconductor substrate at a bottom of the first trench formed in a surface of the semiconductor substrate. A second impurity diffusion area is formed in the surface of the semiconductor substrate, each have one end contacting a first side wall of the first trench, and each have the same conductive type as the first impurity diffusion area. A first gate electrode is provided on the first side wall between the first and second impurity diffusion areas with a gate insulating film interposed therebetween. A first ferroelectric film is provided on a first lower electrode, which is provided on the second impurity area. A first upper electrode is provided on the first ferroelectric film. A first interconnection layer is provided above the first upper electrode. A first contact plug electrically connects the first interconnection layer and first impurity diffusion area.

摘要翻译： 在形成于半导体衬底的表面中的第一沟槽的底部的半导体衬底中形成第一杂质扩散区。 在半导体基板的表面形成第二杂质扩散区域，每个第一杂质扩散区域的一端与第一沟槽的第一侧壁接触，并且各自具有与第一杂质扩散区域相同的导电类型。 第一栅电极设置在第一和第二杂质扩散区之间的第一侧壁上，其间插入有栅极绝缘膜。 第一铁电体膜设置在设置在第二杂质区域上的第一下部电极上。 第一上电极设置在第一铁电体膜上。 第一互连层设置在第一上电极上方。 第一接触插塞电连接第一互连层和第一杂质扩散区。

公开(公告)号：US6153476A

公开(公告)日：2000-11-28

申请号：US30127

申请日：1998-02-25

申请人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumasa Sunouchi

发明人： Satoshi Inaba ,  Tohru Ozaki ,  Yusuke Kohyama ,  Kazumasa Sunouchi

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/088 ,  H01L27/105 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10844 ,  H01L27/105 ,  H01L27/108 ,  Y10S257/90

摘要： In a DRAM, a plurality of first MOSFETs are formed in a cell region on a semiconductor substrate based on the minimum design rule, and a first gate side-wall having a side-wall insulation film is formed on the side-wall portion of a first gate electrode of each of the first MOSFETs. At least one second MOSFET is formed in a peripheral circuit region on the semiconductor substrate, and a second gate side-wall having side-wall insulation films is formed on the side-wall portion of a second gate electrode of the second MOSFET. Both the first MOSFETs, which is capable of forming a fine contact hole self-aligned with the first gate electrode, and the second MOSFET, which is capable of sufficiently mitigating the parasitic resistance while suppressing the short channel effect, can be formed on the same substrate.

公开(公告)号：US5698869A

公开(公告)日：1997-12-16

申请号：US527515

申请日：1995-09-13

申请人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

发明人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L31/072

CPC分类号： H01L29/66666 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78681

摘要： A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

摘要翻译： 提供半导体器件的结构及其制造方法，其中可以减小漏电流，同时改善诸如MOSFET，MOSSIT和MISFET的绝缘栅晶体管的漏极击穿电压，以及保持特性 可以提高诸如使用这些晶体管的DRAM作为开关晶体管的存储单元，并且还可以提高传输栅极中的栅极氧化膜的可靠性。 更具体地，在SOI.IG器件中的源极区域或漏极区域的内部形成诸如SixGe1-x，SixSn1-x，PbS的窄带隙半导体区域。 通过选择SOI膜中的窄带隙半导体区域的位置和/或摩尔分数，或者选择一种杂质元素来补偿由于窄带隙半导体区域引起的晶格失配，可以抑制晶体缺陷的产生 。 此外，即使产生晶体缺陷，也可以抑制晶体缺陷对晶体管的影响或漏电流等存储特性的结构。

公开(公告)号：US5602772A

公开(公告)日：1997-02-11

申请号：US308926

申请日：1994-09-20

申请人： Hiroaki Nakano ,  Daisaburo Takashima ,  Tohru Ozaki

发明人： Hiroaki Nakano ,  Daisaburo Takashima ,  Tohru Ozaki

IPC分类号： G11C11/4097 ,  H01L23/522 ,  H01L27/108 ,  C11C5/02

CPC分类号： G11C11/4097 ,  H01L23/5222 ,  H01L27/10805 ,  H01L2924/0002

摘要： A dynamic semiconductor memory device according to the present invention, comprises a plurality of first bit lines, a plurality of second bit lines which are partially laminated above the first bit lines and, together with the first bit lines, form bit-line pairs to build a folded bit-line structure, a plurality of word lines arranged so as to cross the first bit lines and the second bit lines, and at least one memory cell array in which a plurality of memory cells connected to the first bit lines and the second bit lines are arranged in a matrix, wherein the memory cell array includes a plurality of first areas in which a plurality of memory cells are arranged, and a plurality of second memory areas which are arranged so as to alternate with the first areas and contain no memory cell, and the second memory areas include areas where the first bit lines of the specified number of the bit-line pairs are connected to the second bit lines and the second bit lines are connected to the first bit lines.

公开(公告)号：US5119155A

公开(公告)日：1992-06-02

申请号：US619616

申请日：1990-11-29

申请人： Katsuhiko Hieda ,  Tohru Ozaki

发明人： Katsuhiko Hieda ,  Tohru Ozaki

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10829

摘要： In a semiconductor memory device, a trench is formed in a surface of a memory cell forming region of the substrate. The overall surface of the memory cell forming region, inclusive of the inner wall of the trench, is covered with an insulator film. A capacitor is formed on the inner surface of the trench through the insulator film. A MOSFET is formed in a semiconductor layer formed on a surface of a flat portion of the substrate. One of the source and drain regions of the MOSFET reaches the periphery of the trench so as to be connected to a storage node electrode of the capacitor.

摘要翻译： 在半导体存储器件中，在衬底的存储单元形成区域的表面上形成沟槽。 存储单元形成区域的整个表面（包括沟槽的内壁）被绝缘膜覆盖。 通过绝缘膜在沟槽的内表面上形成电容器。 MOSFET形成在形成在基板的平坦部分的表面上的半导体层中。 MOSFET的源极和漏极区域之一到达沟槽的周边，以便连接到电容器的存储节点电极。

公开(公告)号：US20120001331A1

公开(公告)日：2012-01-05

申请号：US13051652

申请日：2011-03-18

申请人： Takayuki Toba ,  Tohru Ozaki ,  Toshiki Hisada ,  Hiromitsu Mashita ,  Takafumi Taguchi

发明人： Takayuki Toba ,  Tohru Ozaki ,  Toshiki Hisada ,  Hiromitsu Mashita ,  Takafumi Taguchi

IPC分类号： H01L23/485 ,  H01L21/28

CPC分类号： H01L21/76816 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11531 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes a plurality of first interconnects, a second interconnect, a third interconnect, and a plurality of conductive members. The plurality of first interconnects are arranged periodically to extend in one direction. The second interconnect is disposed outside a group of the plurality of first interconnects to extend in the one direction. The third interconnect is provided between the group and the second interconnect. The plurality of conductive members are disposed on a side opposite to the group as viewed from the second interconnect. A shortest distance between the first interconnect and the third interconnect, a shortest distance between the third interconnect and the second interconnect, and a shortest distance between the first interconnects are equal. A shortest distance between the second interconnect and the conductive member is longer than the shortest distance between the first interconnects.

摘要翻译： 根据一个实施例，半导体器件包括多个第一互连，第二互连，第三互连和多个导电构件。 多个第一互连周期性地布置成在一个方向上延伸。 第二互连设置在多个第一互连的一组之外，以在一个方向上延伸。 第三互连设置在组和第二互连之间。 多个导电构件设置在从第二互连件观察的与组相反的一侧上。 第一互连和第三互连之间的最短距离，第三互连和第二互连之间的最短距离以及第一互连之间的最短距离相等。 第二互连和导电构件之间的最短距离比第一互连之间的最短距离长。

公开(公告)号：US07573084B2

公开(公告)日：2009-08-11

申请号：US11898949

申请日：2007-09-18

申请人： Yoshinori Kumura ,  Tohru Ozaki ,  Iwao Kunishima

发明人： Yoshinori Kumura ,  Tohru Ozaki ,  Iwao Kunishima

IPC分类号： H01L27/108

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/57

摘要： According to an aspect of the present invention, there is provided a non-volatile semiconductor memory device, including a ferroelectric capacitor being stacked a first electrode, a ferroelectric film and a second electrode in order, a first protective film with hydrogen barrier performance, the first protective film being formed under the first electrode and on a side-wall of the ferroelectric capacitor, the first protective film being widened from the second electrode towards the first electrode, a second protective film with hydrogen barrier performance, the second protective film being formed over the second electrode and on the first protective film formed on the side-wall of the ferroelectric capacitor, the second protective film being widened from the first electrode towards the second electrode, a cell transistor, a source of the cell transistor being connected to the first electrode, a drain of the cell transistor being connected to a bit line and a gate being connected to a word line.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括堆叠第一电极，铁电体膜和第二电极的铁电电容器，具有氢阻挡性能的第一保护膜， 第一保护膜形成在第一电极下方和铁电电容器的侧壁上，第一保护膜从第二电极朝向第一电极加宽，具有氢阻挡性能的第二保护膜，形成第二保护膜 在第二电极上以及形成在铁电电容器的侧壁上的第一保护膜上，第二保护膜从第一电极朝向第二电极加宽，单元晶体管，单元晶体管的源极连接到 第一电极，单元晶体管的漏极连接到位线，栅极连接到aw ord行。

公开(公告)号：US20090095993A1

公开(公告)日：2009-04-16

申请号：US12244210

申请日：2008-10-02

申请人： Tohru Ozaki ,  Yoshinori Kumura

发明人： Tohru Ozaki ,  Yoshinori Kumura

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/57

摘要： According to an aspect of the present invention, there is provided a semiconductor memory device including a ferroelectric capacitor, including a semiconductor substrate, a transistor having diffusion layers being a source and a drain, the transistor being formed on a surface of the semiconductor substrate, a ferroelectric capacitor being formed over the transistor, the ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode stacked in order, an interlayer insulator separating between the transistor and the ferroelectric capacitor, a first contact plug being embedded in the interlayer insulator formed beneath the ferroelectric capacitor, the first contact plug directly connecting between one of the diffusion layers and the lower electrode, a first hydrogen barrier film covering the transistor a second hydrogen barrier film, a portion of the second hydrogen barrier film being formed on the first hydrogen barrier film, another portion of the second hydrogen barrier film covering at least the ferroelectric capacitor, and a second contact plug being embedded in the interlayer insulator, the second hydrogen barrier film and the first hydrogen barrier film, one end of the second contact plug connecting to the other of the diffusion layers.

摘要翻译： 根据本发明的一个方面，提供了一种包括具有半导体衬底的铁电电容器，具有源极和漏极的扩散层的晶体管的半导体存储器件，晶体管形成在半导体衬底的表面上， 形成在晶体管上的强电介质电容器，所述强电介质电容器包括下电极，强电介质膜和依次堆叠的上电极，分隔在所述晶体管和所述铁电电容器之间的层间绝缘体，第一接触插塞嵌入所述层间绝缘体 形成在强电介质电容器下方的第一接触插塞，直接连接在一个扩散层和下电极之间的第一接触插塞，第一氢阻挡膜，覆盖晶体管第二氢阻挡膜，第二氢阻挡膜的一部分形成在第一 氢屏障膜，另一部分的secon d氢屏障膜，其至少覆盖所述铁电电容器，以及第二接触插塞，其被嵌入在所述层间绝缘体中，所述第二氢阻挡膜和所述第一氢阻挡膜，所述第二接触插塞的一端连接到所述扩散层中的另一个 。

公开(公告)号：US20080230818A1

公开(公告)日：2008-09-25

申请号：US12053137

申请日：2008-03-21

申请人： Yoshinori Kumura ,  Tohru Ozaki ,  Iwao Kunishima

发明人： Yoshinori Kumura ,  Tohru Ozaki ,  Iwao Kunishima

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： According to an aspect of the present invention, there is provided a non-volatile memory including: a transistor formed on a semiconductor substrate, the transistor including: two diffusion layers and a gate therebetween; a first insulating film formed on a top and a side surfaces of the gate; a first and a second contact plugs formed on corresponding one of the diffusion layers to contact the first insulating film; a ferroelectric capacitor formed on the first contact plug and on the first insulating film, the ferroelectric capacitor including: a first and a second electrodes and a ferroelectric film therebetween; a third contact plug formed on the second electrode; and a fourth contact plug formed on the second contact plug.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性存储器，包括：形成在半导体衬底上的晶体管，所述晶体管包括：两个扩散层和栅极; 形成在栅极的顶部和侧表面上的第一绝缘膜; 第一和第二接触塞形成在相应的一个扩散层上以接触第一绝缘膜; 形成在所述第一接触插塞和所述第一绝缘膜上的强电介质电容器，所述强电介质电容器包括：第一和第二电极及其间的铁电体膜; 形成在所述第二电极上的第三接触插塞; 以及形成在所述第二接触插塞上的第四接触插塞。

公开(公告)号：US20080173912A1

公开(公告)日：2008-07-24

申请号：US11941291

申请日：2007-11-16

申请人： Yoshinori KUMURA ,  Tohru Ozaki ,  Susumu Shuto ,  Yoshiro Shimojo ,  Iwao Kunishima

发明人： Yoshinori KUMURA ,  Tohru Ozaki ,  Susumu Shuto ,  Yoshiro Shimojo ,  Iwao Kunishima

IPC分类号： H01L29/00

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/57 ,  H01L28/65

摘要： A semiconductor device comprising a ferroelectric capacitor having improved reliability is disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a transistor formed on a semiconductor substrate, a ferroelectric capacitor formed above the transistor and comprising a lower electrode, a ferroelectric film and an upper electrode, a first hydrogen barrier film formed over the ferroelectric capacitor, an insulator formed over the first hydrogen barrier film, a contact plug disposed in the insulator and electrically connected with the upper electrode, a second hydrogen barrier film disposed between the contact plug and the insulator continuously, and a wiring connected with the contact plug.

摘要翻译： 公开了一种包括具有改善的可靠性的铁电电容器的半导体器件。 根据本发明的一个方面，提供了一种半导体器件，包括形成在半导体衬底上的晶体管，形成在晶体管上方的铁电电容器，包括下电极，铁电体膜和上电极，第一氢阻挡膜 形成在所述铁电电容器上，形成在所述第一氢阻挡膜上的绝缘体，设置在所述绝缘体中并与所述上电极电连接的接触插塞，连续地配置在所述接触插塞和所述绝缘体之间的第二氢阻挡膜， 与接触插头。