公开(公告)号：US20150357436A1

公开(公告)日：2015-12-10

申请号：US14324252

申请日：2014-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Chia-Jong Liu ,  Yi-Wei Chen ,  Ssu-I Fu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Yen-Liang Wu ,  Man-Ling Lu

IPC: H01L29/66 ,  H01L21/3065 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; performing a first dry etching process to form a recess in the substrate adjacent to the gate structure; and performing a second dry etching process to expand the recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成栅极结构; 执行第一干蚀刻工艺以在所述衬底中邻近所述栅极结构形成凹陷; 以及执行第二干蚀刻工艺以使凹部膨胀。

公开(公告)号：US20150255563A1

公开(公告)日：2015-09-10

申请号：US14195967

申请日：2014-03-04

Applicant: United Microelectronics Corp.

Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Man-Ling Lu ,  Cho-Han Fan ,  Ssu-I Fu ,  Chen-Ming Huang

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/32139 ,  H01L29/6653 ,  H01L29/66795

Abstract: A method for manufacturing a semiconductor device is provided, comprising steps of providing a substrate with an underlying layer formed thereon; forming a gate layer overlying the underlying layer; and forming a multi-layer hard mask layer on the gate layer, and the multi-layer hard mask layer comprising a plurality of material layers and a top hard mask formed on the material layers, wherein the gate layer and the top hard mask contain the same element, such as silicon.

Abstract translation: 提供了一种用于制造半导体器件的方法，包括以下步骤：提供其上形成有底层的衬底; 形成覆盖下层的栅极层; 以及在所述栅极层上形成多层硬掩模层，所述多层硬掩模层包括多个材料层和形成在所述材料层上的顶部硬掩模，其中所述栅极层和所述顶部硬掩模含有 相同的元素，如硅。

公开(公告)号：US20150093870A1

公开(公告)日：2015-04-02

申请号：US14042224

申请日：2013-09-30

Applicant: United Microelectronics Corp.

Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/28 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/31111 ,  H01L21/3086 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device structure is provided. The method includes the following step. A gate dielectric layer is formed on a substrate. A gate electrode is on the gate dielectric layer. The gate dielectric layer exposed by the gate electrode is treated. A first etching process is performed to remove at least a portion of the gate dielectric layer exposed by the gate electrode. A spacer is formed on the sidewall of the gate electrode. A second etching process is performed to form recesses in the substrate beside the gate electrode. Besides, during the first etching process and the second etching process, an etching rate of the treated gate dielectric layer is greater than an etching rate of the untreated gate dielectric layer.

Abstract translation: 提供一种制造半导体器件结构的方法。 该方法包括以下步骤。 在基板上形成栅极电介质层。 栅极电极位于栅极电介质层上。 处理由栅电极露出的栅介电层。 执行第一蚀刻工艺以去除由栅电极暴露的栅介质层的至少一部分。 在栅电极的侧壁上形成间隔物。 执行第二蚀刻工艺以在栅电极旁边的基板中形成凹部。 此外，在第一蚀刻工艺和第二蚀刻工艺期间，经处理的栅极电介质层的蚀刻速率大于未处理的栅极介电层的蚀刻速率。

公开(公告)号：US20150035069A1

公开(公告)日：2015-02-05

申请号：US13954991

申请日：2013-07-31

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chien-Ting Lin ,  Po-Chao Tsao ,  Chung-Fu Chang ,  Cheng-Guo Chen

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/1211 ,  H01L21/845

Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure in the substrate; forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure; forming a first gate structure on the STI and the fin-shaped structure; and removing a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure.

Abstract translation: 公开了一种用于制造鳍状场效应晶体管（FinFET）的方法。 该方法包括以下步骤：提供衬底; 在基板中形成翅片状结构; 在衬底上并在鳍状结构的底部周围形成浅沟槽隔离（STI）; 在STI和鳍状结构上形成第一栅极结构; 以及去除STI的一部分以暴露在第一栅极结构下方的STI的侧壁。

公开(公告)号：US20140175527A1

公开(公告)日：2014-06-26

申请号：US13727540

申请日：2012-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Yu-Hsiang Hung ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure.

Abstract translation: 半导体结构包括栅极，双间隔物和两个凹槽。 门位于基板上。 双垫片位于栅极旁边的基板上。 所述凹部位于所述基板和所述双间隔件中，其中所述凹槽旁边的所述凹部的侧壁具有下端部和上端部，并且所述下端部位于所述基板中，而所述上端部为锐角 位于双垫片中并靠近基板。 本发明还提供一种形成所述半导体结构的半导体工艺。

公开(公告)号：US12211915B2

公开(公告)日：2025-01-28

申请号：US18115780

申请日：2023-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Jung Han ,  Ming-Chi Li ,  Chih-Mou Lin ,  Yu-Hsiang Hung ,  Yu-Hsiang Lin ,  Tzu-Lang Shih

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

公开(公告)号：US20240194738A1

公开(公告)日：2024-06-13

申请号：US18587981

申请日：2024-02-27

Applicant: UNITED MICROELECTRONICS CORP

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/665

Abstract: A semiconductor device includes a gate structure on a substrate, a spacer around the gate structure, and a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

公开(公告)号：US11189695B2

公开(公告)日：2021-11-30

申请号：US16703780

申请日：2019-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

公开(公告)号：US20190172752A1

公开(公告)日：2019-06-06

申请号：US15830008

申请日：2017-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chi-Ting Wu ,  Yu-Hsiang Lin

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/768 ,  H01L23/535 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823475 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823468 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate; removing part of the ILD layer between the first metal gate and the second metal gate to form a recess; forming a first spacer and a second spacer in the a recess; performing a first etching process to form a first contact hole; and performing a second etching process to extend the first contact hole into a second contact hole.

公开(公告)号：US09870951B2

公开(公告)日：2018-01-16

申请号：US15599430

申请日：2017-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L23/535 ,  H01L27/088 ,  H01L23/485

CPC classification number: H01L21/823475 ,  H01L21/0206 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/0226 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7856

Abstract: A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate. The substrate between two gate structures is exposed. A silicon oxide layer is formed to cover the exposed substrate. A nitride-containing material layer covers each gate structure and silicon oxide layer. Later, the nitride-containing material layer is etched to form a first self-aligned spacer on a sidewall of each gate structure and part of the silicon oxide layer is exposed, wherein the sidewalls are opposed to each other. Then, the exposed silicon oxide layer is removed to form a second self-aligned spacer. The first self-aligned spacer and the second self-aligned spacer cooperatively define a recess on the substrate. Finally, a contact plug is formed in the recess.