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公开(公告)号：US20240206192A1
公开(公告)日：2024-06-20
申请号：US18595363
申请日：2024-03-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ; forming a passivation layer around the MTJ; forming a second SOT layer on the first SOT layer and the passivation layer, and patterning the second SOT layer and the passivation layer.
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公开(公告)号：US20240032441A1
公开(公告)日：2024-01-25
申请号：US17892162
申请日：2022-08-22
Applicant: United Microelectronics Corp.
Inventor： Chih-Wei Kuo , Hung-Chan Lin , Chung Yi Chiu
CPC classification number: H01L43/04 , H01L27/222 , H01L43/06 , H01L43/10 , H01L43/14
Abstract: Provided is a magnetoresistive random access memory (MRAM) device including a bottom electrode, a magnetic tunnel junction (MTJ) structure, a first spin orbit torque (SOT) layer, a cap layer, a second SOT layer, an etch stop layer, and an upper metal line layer. The MTJ structure is disposed on the bottom electrode. The first SOT layer is disposed on the MTJ structure. The cap layer is disposed on the first SOT layer. The second SOT layer is disposed on the cap layer. The etch stop layer is disposed on the second SOT layer. The upper metal line layer penetrates though the etch stop layer and is landed on the second SOT layer.
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公开(公告)号：US20230097481A1
公开(公告)日：2023-03-30
申请号：US17518571
申请日：2021-11-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Chien-Ting Lin
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ stack; forming a first hard mask on the first SOT layer; and using a second hard mask to pattern the first hard mask, the first SOT layer, and the MTJ stack to form a MTJ.
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公开(公告)号：US20220199897A1
公开(公告)日：2022-06-23
申请号：US17692203
申请日：2022-03-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A magnetoresistive random access memory, including a substrate, a conductive plug in the substrate, wherein the conductive plug has a notched portion on one side of the upper edge of the conductive plug, and a magnetic memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction on the bottom electrode and a top electrode on the magnetic tunnel junction, wherein the bottom surface of the magnetic memory cell and the top surface of the conductive plug completely align and overlap each other.
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公开(公告)号：US20200013949A1
公开(公告)日：2020-01-09
申请号：US16056551
申请日：2018-08-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ya-Sheng Feng , Hung-Chan Lin , Yu-Ping Wang , Yu-Chun Chen , Chiu-Jung Chiu
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the first IMD layer; forming a liner on the MTJ and the first IMD layer; removing part of the liner to form a spacer adjacent to the MTJ; and forming a second IMD layer on the first IMD layer.
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Patent Agency Ranking
16.发明申请SEMICONDUCTOR DEVICE HAVING METAL GATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING METAL GATE 审中-公开具有金属门的半导体器件和用于制造具有金属栅的半导体器件的方法公开(公告)号：US20160315171A1
公开(公告)日：2016-10-27
申请号：US14727853
申请日：2015-06-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Hsiang Hung , Chao-Hung Lin , Chih-Kai Hsu , Ssu-I Fu , Jyh-Shyang Jenq , Jun-Jie Wang , En-Chiuan Liou , Chih-Wei Yang , Chih-Sen Huang , Ching-Wen Hung , Hung-Chan Lin , Yu-Hsiang Lin
IPC: H01L29/66 , H01L29/49 , H01L29/423 , H01L21/28
CPC classification number: H01L29/66545 , H01L21/28088 , H01L21/28114 , H01L21/823842 , H01L27/092 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/6653
Abstract: A method for manufacturing a semiconductor device having a metal gate includes forming a filling layer and a high-K gate dielectric layer in the first recess between a pair of spacers, wherein the high-K gate dielectric layer and the filling layer are stacked in the first recess sequentially, and an exposed top surface of the high-K gate dielectric layer and a top surface of the filling layer are lower than a top surface of each spacer; and removing a part of each spacer and widening the first recess on the top surface of the filling layer to form a second recess, wherein a width of the second recess is larger than a width of the first recess.
Abstract translation: 一种具有金属栅极的半导体器件的制造方法包括在一对间隔物之间的第一凹部中形成填充层和高K栅极电介质层，其中高K栅极介电层和填充层堆叠在 第一凹部，高K栅极电介质层的露出顶表面和填充层的顶表面比每个间隔物的顶表面低; 并且移除每个间隔物的一部分并加宽填充层的顶表面上的第一凹部以形成第二凹部，其中第二凹部的宽度大于第一凹部的宽度。
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公开(公告)号：US20240215260A1
公开(公告)日：2024-06-27
申请号：US18595376
申请日：2024-03-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a passivation layer around the MTJ, and a second SOT layer on the first SOT layer and the passivation layer. Preferably, a top surface of the passivation layer is lower than a top surface of the first SOT layer.
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公开(公告)号：US11968910B2
公开(公告)日：2024-04-23
申请号：US17500971
申请日：2021-10-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Chien-Ting Lin
Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming an etch stop layer on the MTJ stack, forming a first spin orbit torque (SOT) layer on the etch stop layer, and then patterning the first SOT layer, the etch stop layer, and the MTJ stack to form a MTJ.
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公开(公告)号：US20240107777A1
公开(公告)日：2024-03-28
申请号：US17964935
申请日：2022-10-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Hung-Chan Lin , Chung-Yi Chiu
CPC classification number: H01L27/228 , H01L43/04 , H01L43/06 , H01L43/14
Abstract: An SOT MRAM structure includes a word line. A second source/drain doping region and a fourth source/drain doping region are disposed at the same side of the word line. A first conductive line contacts the second source/drain doping region. A second conductive line contacts the fourth source/drain doping region. The second conductive line includes a third metal pad. A memory element contacts an end of the first conductive line. A second SOT element covers and contacts a top surface of the memory element. The third metal pad covers and contacts part of the top surface of the second SOT element.
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公开(公告)号：US20230200258A1
公开(公告)日：2023-06-22
申请号：US17574569
申请日：2022-01-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin
CPC classification number: H01L43/14 , H01L27/222 , H01L43/04 , H01L43/06
Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic random access memory (MRAM) region and a logic region, forming a first inter-metal dielectric (1MB) layer on the substrate, forming a first metal interconnection and a second metal interconnection in the first IMD layer on the MRAM region, forming a spin orbit torque (SOT) layer on the first metal interconnection and the second metal interconnection, forming a magnetic tunneling junction (MTJ) stack on the SOT layer, forming a hard mask on the MTJ stack, using the hard mask to pattern the MTJ stack for forming the MTJ, forming the cap layer on the SOT layer and the hard mask, and patterning the cap layer and the SOT layer.
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