公开(公告)号：US20200227625A1

公开(公告)日：2020-07-16

申请号：US16261524

申请日：2019-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yi-Wei Tseng ,  Meng-Jun Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  I-Ming Tseng

IPC: H01L43/02 ,  H01L27/22

Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.

公开(公告)号：US10658458B2

公开(公告)日：2020-05-19

申请号：US16028386

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Chun-Hsien Lin ,  Wen-An Liang

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: A method of forming a semiconductor structure is disclosed. A fin structure is formed on a substrate and a trench is formed in the fin structure. The trench has a top corner, an upper portion having an upper sidewall and a lower portion having a lower sidewall. A first dielectric layer is then formed on the substrate and fills the lower portion of the trench. After that, a second dielectric layer is formed on the substrate and covers the top corner and the upper sidewall of the trench. The second dielectric layer also covers an upper surface of the first dielectric layer.

公开(公告)号：US10607897B2

公开(公告)日：2020-03-31

申请号：US16589032

申请日：2019-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Ching-Ling Lin ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Wen-An Liang ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Yuan-Yu Chung ,  I-Ming Tseng

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.

公开(公告)号：US10043868B2

公开(公告)日：2018-08-07

申请号：US15249462

申请日：2016-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Chun-Hsien Lin ,  Wen-An Liang

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure and method of forming the same. The semiconductor structure includes a fin structure formed on a substrate and an isolation structure formed therein. The isolation structure includes a trench with a concave upper sidewall, a straight lower sidewall and a rounded top corner. A first dielectric layer fills a lower portion of the trench. A second dielectric layer covers a top surface of the first dielectric layer, the concave upper sidewall and the rounded top corner of the trench.

公开(公告)号：US09859147B2

公开(公告)日：2018-01-02

申请号：US15336811

申请日：2016-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tong-Jyun Huang ,  Rai-Min Huang ,  I-Ming Tseng ,  Kuan-Hsien Li ,  Chen-Ming Huang

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/02 ,  H01L27/088 ,  H01L21/3065

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.

公开(公告)号：US09607985B1

公开(公告)日：2017-03-28

申请号：US14864908

申请日：2015-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L21/70 ,  H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/3081 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a plurality of fin shaped structures, a first trench and at least one bump. The substrate has a base. The fin shaped structures protrude from the base of the substrate. The first trench recesses from the base of the substrate and has a depth being smaller than a width of each of the fin shaped structures. The at least one bump is disposed on a surface of the first trench.

公开(公告)号：US20170012000A1

公开(公告)日：2017-01-12

申请号：US14844004

申请日：2015-09-03

Applicant: United Microelectronics Corp.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L23/535 ,  H01L29/16 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device including a fin structure, a first liner, a first insulating layer and a dummy gate structure. The fin structure is disposed on a substrate, where the fin structure has a trench. The first liner disposed in the trench. The first insulating layer disposed on the first liner. The dummy gate structure is disposed on the first insulating layer and disposed above the trench, where a bottom surface of the dummy gate and a top surface of the fin structure are on a same level.

Abstract translation: 一种半导体器件及其制造方法，所述半导体器件包括翅片结构，第一衬垫，第一绝缘层和虚拟栅极结构。 翅片结构设置在基板上，其中鳍结构具有沟槽。 布置在沟槽中的第一个衬垫。 第一绝缘层设置在第一衬垫上。 虚拟栅极结构设置在第一绝缘层上并且设置在沟槽上方，其中虚拟栅极的底表面和鳍状结构的顶表面处于同一水平面上。

公开(公告)号：US20160293726A1

公开(公告)日：2016-10-06

申请号：US14710602

申请日：2015-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rai-Min Huang ,  I-Ming Tseng ,  Tong-Jyun Huang ,  Kuan-Hsien Li

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/027 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/66545 ,  H01L21/3086 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/6656 ,  H01L29/785

Abstract: A patterned structure of a semiconductor device includes a substrate, a first feature and a second feature. The first feature and the second feature are disposed on the substrate, and either of which includes a vertical segment and a horizontal segment. There is a distance between the vertical segment of the first feature and the vertical segment of the second feature, and the distance is less than the minimum exposure limits of an exposure apparatus.

Abstract translation: 半导体器件的图案化结构包括衬底，第一特征和第二特征。 第一特征和第二特征设置在基板上，并且其中之一包括垂直段和水平段。 在第一特征的垂直段和第二特征的垂直段之间存在距离，并且该距离小于曝光设备的最小曝光极限。

公开(公告)号：US20240357943A1

公开(公告)日：2024-10-24

申请号：US18760005

申请日：2024-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Jung Chiu ,  Ya-Sheng Feng ,  I-Ming Tseng ,  Yi-An Shih ,  Yu-Chun Chen ,  Yi-Hui Lee ,  Chung-Liang Chu ,  Hsiu-Hao Hu

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

公开(公告)号：US20240032439A1

公开(公告)日：2024-01-25

申请号：US18373295

申请日：2023-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Kun-Chen Ho ,  Yi-Syun Chou ,  Chang-Min Li ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  JUN XIE

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.