公开(公告)号：US10700202B2

公开(公告)日：2020-06-30

申请号：US16172856

申请日：2018-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Sung-Yuan Tsai ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Chao-Nan Chen ,  Shi-You Liu ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.

公开(公告)号：US10460925B2

公开(公告)日：2019-10-29

申请号：US15639381

申请日：2017-06-30

Applicant: United Microelectronics Corp.

Inventor： Hsu Ting ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L21/311 ,  H01L29/66

Abstract: A method for processing a semiconductor device is provided. The semiconductor device includes a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure. The method includes removing the nitride spacer on the protruding structure. Then, a dilute hydrofluoric (DHF) cleaning process is performed over the substrate, wherein a top surficial portion of the epitaxial layer is removed. A standard clean (SC) process is performed over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.

公开(公告)号：US20180096995A1

公开(公告)日：2018-04-05

申请号：US15284552

申请日：2016-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/517

Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.

公开(公告)号：US09871113B2

公开(公告)日：2018-01-16

申请号：US15064275

申请日：2016-03-08

Applicant: United Microelectronics Corp.

Inventor： Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L21/266 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/66492 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66636

Abstract: A semiconductor process including the following steps is provided. An epitaxial layer is formed on a substrate. An oxide layer is formed on the epitaxial layer, wherein the oxide layer includes a chemical oxide layer, a high-temperature oxide (HTO) layer or a surface modification oxide layer. An ion implant process is performed to the epitaxial layer to form a doped region in the epitaxial layer. The oxide layer is removed by using a diluted hydrofluoric acid (DHF) solution after performing the ion implant process, wherein a volume ratio of water to a hydrofluoric acid (HF) in the DHF solution is 200:1 to 1000:1.

公开(公告)号：US20170221723A1

公开(公告)日：2017-08-03

申请号：US15012821

申请日：2016-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L21/321 ,  H01L21/3105 ,  H01L21/283 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3205

CPC classification number: H01L21/3212 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/283 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/32055 ,  H01L21/32115 ,  H01L29/66795

Abstract: A method for fabricating a semiconductor structure includes following steps. First, a first layer, a second layer and a third layer are sequentially formed on the substrate. The second layer is conformally disposed on the top surface of the first layer. The second layer and the first layer have different compositions, and the third layer and the second layer also have different compositions. Then, a planarizing process is performed on the third layer until portions of the second layer are exposed. Afterwards, hydrofluoric acid and aqueous oxidant are concurrently or sequentially provided to the remaining second and third layers. Finally, an etch back process is carried out to remove all the second layer and portions of the first layer.

公开(公告)号：US12300743B2

公开(公告)日：2025-05-13

申请号：US18665600

申请日：2024-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

公开(公告)号：US11735661B2

公开(公告)日：2023-08-22

申请号：US17330443

申请日：2021-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Sung-Yuan Tsai ,  Chi-Hsuan Tang ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

公开(公告)号：US11049971B2

公开(公告)日：2021-06-29

申请号：US16205233

申请日：2018-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Sung-Yuan Tsai ,  Chi-Hsuan Tang ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

公开(公告)号：US10651174B2

公开(公告)日：2020-05-12

申请号：US16412337

申请日：2019-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/51

Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.

公开(公告)号：US20190279979A1

公开(公告)日：2019-09-12

申请号：US16412337

申请日：2019-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L21/8234

Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.