公开(公告)号：US20210134979A1

公开(公告)日：2021-05-06

申请号：US16670890

申请日：2019-10-31

Applicant: United Microelectronics Corp.

Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

IPC: H01L29/66 ,  H01L27/1157

Abstract: A method for fabricating gate structures includes providing a substrate, configured to have a first region and a second region. Dummy gate structures are formed on the substrate at the first and second regions, wherein each of the dummy gate structures has a first gate insulating layer on the substrate and a dummy gate on the first gate insulating layer. An inter-layer dielectric layer is formed over the dummy gate structures. The inter-layer dielectric layer is polished to expose all of the dummy gates. The dummy gates are removed. The first gate insulating layer at the second region is removed. A second gate insulating layer is formed on the substrate at the second region, wherein the first gate insulating layer is thicker than the second insulating layer. Metal gates are formed on the first and the second insulating layer.

公开(公告)号：US10580780B2

公开(公告)日：2020-03-03

申请号：US16005422

申请日：2018-06-11

Applicant: United Microelectronics Corp.

Inventor： Zi-Jun Liu ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Hung-Wei Lin ,  An-Hsiu Cheng ,  Chih-Hao Pan ,  Cheng-Hua Chou ,  Chih-Hung Wang

IPC: H01L23/62 ,  H01L27/112 ,  H01L27/11521 ,  H01L27/1156 ,  H01L21/762 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/28

Abstract: Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.

公开(公告)号：US10340282B1

公开(公告)日：2019-07-02

申请号：US15895886

申请日：2018-02-13

Applicant: United Microelectronics Corp.

Inventor： Shu-Hung Yu ,  Chun-Hung Cheng ,  Chuan-Fu Wang ,  An-Hsiu Cheng ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Chia-Hui Huang ,  Chih-Yao Wang ,  Zi-Jun Liu ,  Chih-Hao Pan

IPC: H01L21/18 ,  H01L27/1157 ,  H01L21/762 ,  H01L23/528 ,  H01L29/06

Abstract: A semiconductor memory device includes a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction. A plurality of STI structures is disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions. A selection gate line is extending along a second direction and crossing over the cell regions and the STI structures. A control gate line is adjacent to the selection gate line in parallel extending along the second direction and also crosses over the cell regions and the STI structures. The selection gate line and the control gate line together form a two-transistor (2T) memory cell.

公开(公告)号：US09412851B2

公开(公告)日：2016-08-09

申请号：US14138153

申请日：2013-12-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Kun-I Chou ,  Chung-Che Huang ,  Chia-Cheng Hsu ,  Mu-Jia Liu

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成图案化的多层电介质膜; 在图案化的多层电介质膜上形成图案化的叠层，使得图案化的多层电介质膜的边缘从图案化的叠层露出; 形成覆盖层以覆盖基板的一部分并暴露图案化的叠层和图案化多层电介质膜的暴露边缘; 通过使用覆盖层和图案化叠层作为蚀刻掩模去除图案化的多层电介质膜的暴露边缘的至少一部分; 以及通过使用覆盖层作为蚀刻掩模进行离子注入工艺以形成掺杂区域。

公开(公告)号：US11600709B2

公开(公告)日：2023-03-07

申请号：US17853954

申请日：2022-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

公开(公告)号：US20220271137A1

公开(公告)日：2022-08-25

申请号：US17219829

申请日：2021-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

IPC: H01L29/423 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

公开(公告)号：US11362186B2

公开(公告)日：2022-06-14

申请号：US16831846

申请日：2020-03-27

Applicant: United Microelectronics Corp.

Inventor： Kuo-Lung Li ,  Chih-Hao Pan ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chi-Cheng Huang

IPC: H01L29/423 ,  H01L27/1157 ,  H01L29/66 ,  H01L27/11573 ,  H01L29/792 ,  H01L21/28

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a first gate structure disposed on the substrate, a second gate structure disposed on the substrate, and a memory gate structure disposed on the substrate and between the first gate structure and the second gate structure. The memory gate structure at least covers the first gate structure and the second gate structure. The memory gate structure includes a charge storage layer disposed on the substrate and a memory gate layer disposed on the charge storage layer.

公开(公告)号：US20210265474A1

公开(公告)日：2021-08-26

申请号：US16831846

申请日：2020-03-27

Applicant: United Microelectronics Corp.

Inventor： Kuo-Lung Li ,  Chih-Hao Pan ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chi-Cheng Huang

IPC: H01L29/423 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/66

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a first gate structure disposed on the substrate, a second gate structure disposed on the substrate, and a memory gate structure disposed on the substrate and between the first gate structure and the second gate structure. The memory gate structure at least covers the first gate structure and the second gate structure. The memory gate structure includes a charge storage layer disposed on the substrate and a memory gate layer disposed on the charge storage layer.

公开(公告)号：US20180053771A1

公开(公告)日：2018-02-22

申请号：US15238574

申请日：2016-08-16

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

公开(公告)号：US20150179748A1

公开(公告)日：2015-06-25

申请号：US14138153

申请日：2013-12-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Kun-I Chou ,  Chung-Che Huang ,  Chia-Cheng Hsu ,  Mu-Jia Liu

IPC: H01L29/423 ,  H01L29/66

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成图案化的多层电介质膜; 在图案化的多层电介质膜上形成图案化的叠层，使得图案化的多层电介质膜的边缘从图案化的叠层露出; 形成覆盖层以覆盖基板的一部分并暴露图案化的叠层和图案化多层电介质膜的暴露边缘; 通过使用覆盖层和图案化叠层作为蚀刻掩模去除图案化的多层电介质膜的暴露边缘的至少一部分; 以及通过使用覆盖层作为蚀刻掩模进行离子注入工艺以形成掺杂区域。