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    Fin structure and fin structure cutting process
    11.
    发明授权
    Fin structure and fin structure cutting process 有权
    翅片结构和翅片结构切割过程

    公开(公告)号：US09524909B2

    公开(公告)日：2016-12-20

    申请号：US14696494

    申请日：2015-04-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tong-Jyun Huang ,  Rai-Min Huang ,  I-Ming Tseng ,  Kuan-Hsien Li ,  Chen-Ming Huang

    IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/02 ,  H01L27/088

    CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

    Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.

    Abstract translation: 翅片结构切割过程包括以下步骤。 在基板中形成有四个翅片结构，其中包括第一翅片结构，第二翅片结构，第三翅片结构和第四翅片结构的四个翅片结构彼此顺序并联。 执行第一鳍结构切割处理以去除第二鳍结构和第三鳍结构的顶部部分，从而由第二鳍结构形成第一凸起，以及由第三鳍结构形成的第二凸起。 执行第二鳍结构切割处理以完全去除第二凸起和第四鳍结构，但是将第一凸起保持在第一鳍结构旁边。 此外，本发明提供了一种通过所述方法形成的翅片结构。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    12.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20150162419A1

    公开(公告)日：2015-06-11

    申请号：US14102515

    申请日：2013-12-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yu-Ting Li ,  Po-Cheng Huang ,  Wu-Sian Sie ,  Chun-Hsiung Wang ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Rai-Min Huang

    IPC: H01L29/66 ,  H01L21/321 ,  H01L21/02 ,  H01L21/3205

    CPC classification number: H01L29/66545 ,  H01L21/02074 ,  H01L21/02112 ,  H01L21/02318 ,  H01L21/32055 ,  H01L21/3212 ,  H01L29/66795

    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate including at least a fin structure is provided, and a material layer is formed to cover the fin structure. Then, a first planarization process is performed on the material layer to form a first material layer, and an oxide layer is formed on the first material layer. Subsequently, the oxide layer is totally removed to expose the first material layer, and a second material layer is formed in-situ on the first material layer after totally removing the oxide layer.

    Abstract translation: 制造半导体器件的方法包括以下步骤。 提供至少包括翅片结构的基板，并且形成材料层以覆盖翅片结构。 然后，在材料层上进行第一平面化处理以形成第一材料层，并且在第一材料层上形成氧化物层。 随后，完全除去氧化物层以露出第一材料层，并且在完全除去氧化物层之后，在第一材料层上原位形成第二材料层。

    Semiconductor layout pattern and manufacturing method thereof
    14.
    发明公开
    Semiconductor layout pattern and manufacturing method thereof 审中-公开

    公开(公告)号：US20240365679A1

    公开(公告)日：2024-10-31

    申请号：US18205570

    申请日：2023-06-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： I-Fan Chang ,  Jia-Rong Wu ,  Rai-Min Huang ,  Po-Kai Hsu

    IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

    CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01 ,  G11C11/161

    Abstract: The invention provides a semiconductor layout pattern, which comprises a first metal layer, wherein the first metal layer comprises a plurality of first patterns and a plurality of fishbone line patterns arranged on the same layer, wherein each fishbone line pattern comprises a principal axis pattern extending along a first direction and a plurality of branches arranged along a second direction, and each first pattern is located between two adjacent branches and the principal axis pattern, and a second metal layer is located on the first metal layer. A plurality of magnetic tunnel junction (MTJ) elements located on the second metal layer, wherein each magnetic tunnel junction element is arranged in a rhombic shape.

    SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
    18.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20210013396A1

    公开(公告)日：2021-01-14

    申请号：US16541172

    申请日：2019-08-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Rai-Min Huang

    IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

    Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

    Method for forming fin structures for non-planar semiconductor device
    19.
    发明授权
    Method for forming fin structures for non-planar semiconductor device 有权

    公开(公告)号：US09786502B2

    公开(公告)日：2017-10-10

    申请号：US15067157

    申请日：2016-03-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuan-Hsien Li ,  Rai-Min Huang ,  I-Ming Tseng ,  Wen-An Liang ,  Chen-Ming Huang

    IPC: H01L21/033 ,  H01L21/8234

    CPC classification number: H01L21/0337 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/6681

    Abstract: A method for forming fin structure includes following steps. A substrate is provided. A first mandrel and a plurality of second mandrels are formed on the substrate simultaneously. A plurality of spacers are respectively formed on sidewalls of the first mandrel and the second mandrels and followed by removing the first mandrel and the second mandrels to form a first spacer pattern and a plurality of second spacer patterns. Then the substrate is etched to simultaneously form at least a first fin and a plurality of second fins on the substrate with the first spacer pattern and the second spacer patterns serving as an etching mask. At least one of the second fins is immediately next to the first fin, and a fin width of the first fin is larger than a fin width of the second fins. Then, the second fins are removed from the substrate.

    METHOD FOR FORMING FIN STRUCTURES FOR NON-PLANAR SEMICONDUCTOR DEVICE
    20.
    发明申请
    METHOD FOR FORMING FIN STRUCTURES FOR NON-PLANAR SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20170263454A1

    公开(公告)日：2017-09-14

    申请号：US15067157

    申请日：2016-03-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuan-Hsien Li ,  Rai-Min Huang ,  I-Ming Tseng ,  Wen-An Liang ,  Chen-Ming Huang

    IPC: H01L21/033 ,  H01L21/8234

    CPC classification number: H01L21/0337 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/6681

    Abstract: A method for forming fin structure includes following steps. A substrate is provided. A first mandrel and a plurality of second mandrels are formed on the substrate simultaneously. A plurality of spacers are respectively formed on sidewalls of the first mandrel and the second mandrels and followed by removing the first mandrel and the second mandrels to form a first spacer pattern and a plurality of second spacer patterns. Then the substrate is etched to simultaneously form at least a first fin and a plurality of second fins on the substrate with the first spacer pattern and the second spacer patterns serving as an etching mask. At least one of the second fins is immediately next to the first fin, and a fin width of the first fin is larger than a fin width of the second fins. Then, the second fins are removed from the substrate.

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